PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT.

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

triggers state generator U34 causing

FSAS-P to go h i g h a n d F S A T - N t o g o l o w .

When FSAS-P goes high, G7 is acti-

vaated which resets FF4. FSAS-P also

clears FF11 if it was set. FSAT-N

causes FSHR-N to go low for 10.25

usec to allow for possible address regis-

ter incrementation The second posi-

tive going edge out of I3, triggers state

generator U34 a second time causing

FSAS-P to go low and FSAT-N to go high.

When FSHR-N goes high, FF3 is set

activating G4 which activates G5. The

next positive going edge out of I3

triggers state generator U34 causing

FSRS-P to go high and FSBR-N to go

l o w . The output of I2, FSBR-N, pre-

sets FF5 which disables G5. The

second positive going edge out of I3,

after FSHR-D: goes low, triggers state

generator U34 causing FSBS-P to go

low and FSBR-N to go high.

5 - 7 0 5 . While FSBS-P is high and

FSBR-N is low, OFDN-N, IFND-N,

lFWl-N, 2nd FWlS-P are generated.

is generated when FSBR-N

OFDN-N

activates G38 which enables G39 to

be activated by CFlA-P. G32 is en-

abled by FSBS-P and activated by

The

CFOA-P which activates G33.

outputs of G39, OFDL-N, and G33,

lFND-N are routed to the Program:

Maintenance Panel INFIBUS access circuit

to gain access to the INFIBUS. FSBS-P

e n a b l e s G 1 1 , G 1 5 , G 1 7 a n d G 1 8 . CF1A-P

activates G15 which ensures FF8 is

CFOA-P

activates

G11,

G17,

cleared.

a n d G18. T h e o u t p u t o f G 1 7 e n s u r e s

FF10 is cleared. The output of G18 pre-

s e t s FF11 w h i c h r e m a i n s preset until

FSAS-P is generated again. FSPS-P en-

ables G31 and FSPR-N disables G27.

The output of G11, 1FW1-N, presets FF2

causing FWlS-P (waveform L, figure 108)

to go high

FHTR-N activates G57 which

enables G51. G49 is enabled by FRNS-P.

FRNR-N activates G58 which enables G59.

When FW1S-P goes high, G49, G51, and

G59 are activated causing RNDB-P and

HTDB-P to go high and CRAB-N to go low.

With ARAB-P and CRAB-N low, the CPU

control register address is strobed to the

INFIBUS address lines when INFIBUS ac-

5-109