PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

gates G11, G13, G15, G17, and G18.

MRES-N, is received by Program Mainte-

CFIA-P activates G15 which ensures FF8 is

nance Panel state generation and micro

cleared. CFOA-P activates gates G11 and

operations circuit or until FSBS-P is gen-

G16, The output of G16 activates G17

erated again which will only occur with

whi

clears FF10 if it was set. The out-

another switch closure on the Program

Maintenance Panel switch flip-flops and

G11, IFW1-N (waveform J, figure

put

single action discriminator circuit. Be-

107), presets FF2 causing FWlS-P (wave-

cause state generator U34 is now in its

form L, figure 107) to go high. FHTR-N

quiescent state (all outputs low), all

activates gates G57 and G58. The output of

operations in the state generation and

G57 enables

1 and the output of G58 en-

micro operations circuits cease until the

ables G59.

en FWlS-P goes high, gates

run or step switch on the Program Mainte-

activated causing HTDB-P

nance Panel switch flip-flops and single

to go high and CRAB-P to go low. With

action discrimination circuit is touched.

ARAB-P and CRAB-N low, the CPU control

5-703. When the run switch on the Pro-

address lines when infibus access is gained

gram Maintenance Panel switch flip-flops

ith HTDB-P high and R DB-P and VADB-P

and single action discriminator circuit is

low, the halt command is strobed to the

touched, operation is similar to when the

INFIBUS data lines when INFIBUS access is

halt switch is touched, except when

gained.

OSTS-P goes high, FRNS-P goes high and

FRNR-N goes low. FRNR-N activates G58

hen the Program Maintenance

5-702.

which enables gate G59 and FRNS-P

PaneI INFIBUS access circuit receives

enables gate G49. When FWlS-P

DONE-N or QUIT-N from the CPU, FDNR-N

goes high, gates G49 and G59 are

or FATR-N goes low. FDNR-N or FATR-N

activated causing RNDB-P to go

activates gate G3 which activates gate G2.

high and CRAB-N to go low. With

The next positive

ing edge out of I3,

ARAB-P and CRAB-N low, the CPU control

after FDNR-N o

R-N goes low, triggers

which causes FSCS-P

address lines when INFIBUS access is

figure 107) to go high.

gained.

B-P high and VADB-P

a c t i v i t e d gates G27 and G40.

The

and HTDB-P low, the run command is

output of G40 is inverted by inverter I15

strobed to the INF

causing OFWl-P (waveform N, figure 107)

S access is

INF

All operations

to go high which clears FF2 and ensures FF1

are

same as w

the halt switch is

is cleared. The output of FF2 now disables

touched, except the Program Maintenance

G2 and the next positive going edge out of

Panel state generation micro operations

I3 causes FSCS-P to go low. The output of

circuit remains in the quiescent state until

G40 also activates G38 which enables

OSTS-P is generated by another switch

G39 to be activated by CFIA-P. The

closure on the Program Maintenance Panel

output of G39, the second OFDN-N

switch flip-flops and single action dis-

pulse is routed to the Program Mainte-

criminator circuit, an address halt is re-

nance Panel INFIBUS access circuit.

recognition occurs.

quired, or an address

The output of gate G27 activates gate G28

which activates gate G29. The output of

G29 is routed to gate G30. FDNS-P also

goes high when DONE-N is received by

the Program Maintenance Panel INFIBUS

access logic circuit which enables G30.

G30 is activated by CF1A-P causing IFAD-N

to go low for one CF1A-P pulse. IFAD-N

The output of FF10 is inverted

by inverter I11, causing BADE-N to go

which lights the done LED CR57. FF1

mains set until a master reset pulse,

5-108