PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT.

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

clock the Program Maintenance Panel mis-

determined by the address 0 through 15

cellaneous control circuit. The divide by

switches. This circuit also causes the

16 output of counter U55 is also inverted

Program Maintenance Panel address to be

by inverter I8, generating CLKI-N which

strobed to the INFIBUS during a level 1

clocks the Program Maintenance Panel ad-

interrupt. In the slave mode (when being

dress/data switch identification, multi-

addressed by another function) this circuit

plexers, and LED circuit.

causes either the address or data switch

closure information to be strobed to the

5-700. Approximately 1.9 msec after the

INFIBUS lines.

halt switch on the Program Maintenance

Panel switch flip-flops and single action

5 - 5 9 8 . Detail Analysis (see figure 106).

discriminator circuit is touched, OSTS-P

Initially, MRES-N is coupled through in-

goes high for 3.4 usec and FHTS-P goes

verter I6. The output of I6 activates gate

high and FHTR-N go low. The trailing edge

G7 which resets flip-flop FF4. The output

of OSTS-P (waveform C, figure 107) sets FF4

of I6 is also inverted by inverter I5 which

(waveform D, figure 107). Inverter I3 in-

resets flip-flops FFl, FF2, FF3, FF5, FF6,

verts the CFOA-P pulses. The first posi-

FF7, FF8, FF9, FF10, and FF11, state

tive going edge out of I3, after OSTS-P

generator U34 and counter U55. MRBA-N,

goes low, triggers the state generator U34

from the Program Maintenance Panel ad-

causing FSAS-P (waveform E, figure 107) to

dress/data switch identification, multi-

go high and FSAT-N to go low. When

plexers, and LED circuit, goes low when-

FSAS-P goes high, G7 is activated which

ever a master reset, MRES-N, is received

resets FF4. FSAS-P also clears FF11 if it

by the Program Maintenance Panel or when

was set. FSAT-N causes FSHR-N (wave-

the address clear switch is touched.

SFSA-N from the Program Maintenance Panel

form F, figure 107) to go low for 10.25

address/data switch identification, multi-

usec to allow for possible address register

incrementation. The second positive going

plexers, and LED circuit, goes low

edge out of I3, triggers the state generator

whenever an address 0 through 15 or data 0

U34 a second time causing FSAS-P to go

through - switch is touched. ANRW-N from

low and FSAT-N to go high. When FSHR-N

the Program Maintenance Panel switch flip-

goes high, FF3 is set, activating G4 which

flops and single action discriminator circuit

activates G5. The next positive going edge

goes low whenever the run,

out of I3 triggers state generator U34,

touched. If MRBA-N or SFSA-N goes low,

causing FSBS-P (waveform G, figure 107) to

gate G24 is activated. The output of G24

go high and FSBR-N to go low via inverter

is inverted by inverter I13. When the out-

I2. The output of I2 presets FF5 which dis-

put of I13 or ANRW-N goes low, gate G25

ables G5. The positive going edge out of

is activated which sets flip-flops FF12 and

I3, after FF5 is preset, triggers state gen-

FFl3.

erator U34 causing FSBS-P to go low and

FSBR-N to go high.

5 - 6 9 9 . The 25 MHZ clock, CLKA-N, from

the INFIBUS IS inverted by inverter I7 which

5 - 7 0 1 . While FSBS-P is high and FSBR-N is

constantly triggers counter U55. The divide

low, OFDN-N, lFND-N, and FWlS-P are

by 4 output of counter U55, IS divided by 2

genera ted. OFDN-N (waveform H, figure

by FF6. The outputs of FF6 alternately en-

107) is generated when FSBR-N activates

able gates G8 and G9 which are activated

gate G38 which enables G39. G39 is acti-

by the divide by 4 output of counter U55.

vated by CFlA-P. Gate G32 is enabled by

The output of G9, CFOA-P (waveform: A,

FSPS-P and activated by CROA-P which acti-

figure 107), and the output of G8, CFIA-P

vates gate G33. T h e o u t p u t s of G39,

(waveform B, figure 107), are used to time

OFDN-N, and G33, lFND-N (waveform I,

operations in the state generation and

fIgure: 107) are routed to the Program Mainte-

nance Panel INFIBUS access circuit to gain

access to the INFIBUS. FSBS-P enables

5-107