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Page Title:
PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT. |
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 T.O.
3lS5-4-308-i
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
msec after SWIT-P goes high OACS-P goes
W-N is also inverted by inverter
output of I6 is routed to FF3 and
ing edge of OACS-P sets FF3 and
FF2 is cleared. The output of FF3
i s inverted by inverter I7 causing FAHL-N
to go Bow, lighting the ad& LED (CR63).
The output of F
FAHS-P, is also routed
to the Program
intenanc Panel state
ro operations circuit
which causes the address halt command to
US data lines and
the CPU conntrol register address to be
to the INFIBUS address lines when
access is gained (when address on
INFIBUS equals address in address shift
register. FF3 remains set until an
pulse is received or another switch
causes OACS-P to be generated.
hew the attn (attention) switch
5-693.
is touched, SATN-N goes low and is
coupled through driver DR3. The low out-
put of DR3 enables gate G6 and activates
gate G5. The output of G5 activates G4
ad the output of G4 is inverted by I
to go high. When S
P goes high and 1.9
T-P goes high
CS-P goes high
CS-P is b-averted by I
for 3 . 4 u s e c .
which activates G6. This low ou
G6 presets flip-flop FF-4 causing
5-696.
go low. 24 msec after the attn s
released, OLTS-P returns to a low level
which resets FF4 causing FTT
to a high level. This Bow-to-high level
transistion of FTTR-N
s the Program
Maintenance Panel IN
access circuit
to generate a level 1 interrupt.
5 - 6 9 4 . When the reset switch S56 is
touched, SRST- goes low and is routed to
the INFIBUS as EPB-N which causes a
master reset pulse, MRES-N, to be gener-
ated by the Bus Controller. SET-N is
coupled through driver DR4 and DR5 ca
REPL-N to go low which causes the reset
LED (CRS8) to light for as long as the reset
switch is touched. The low output of DR4
also activates G5 which causes SWIT-P to
bc generated, as explained previously.
5 - 6 9 5 . When SRLC-N goes low, the out-
put of inverter I10 goes high which causes
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