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Page Title: PROGRAM MAINTENANCE PANEL SWITCH FLIP-FLOPS AND SINGLE ACTION DISGRIMINATOR CIRCUIT-CONT.
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T.O. 31S5-4-308-1
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
Detail Analysis (see figure 105).
5-690.
When the Program Maintenance Panel state
generation and
ceives a maste
MREU-N goes low.
FF2, and FF3.
gate Gl which is activated when FFI resets,
The output of G1 enables gate G2 a
coupled through driver DR1 causing
to go low which lights the
When the load switch (S
SLOD-N goes low activa
of G2 activates gate G4
G3. The output of G4 is
I9 causing S WIT-P to go high. 1.9 msec
after SWIT-P goes high, OACS-P goes
for 3.4 usec and is inverted by inverte
The output of I8 activates G3 and enab
G6.  The output of G3 is
through driver DR2 causing ATL
(autoload) to go low for 3.4
end of any INFIBUS transfer,
the Program Maintenance Pan
access circuit goes high an
inverter I1. The out put of I1 presets FFl
which disables G1, causing
to go out and prevents any f
switch closures front genera
until another master reset p
generated on the INFIBUS.
5-691. When the inh (inhibit
is touched, SIN11
verted by invertcr I4.  The hig
5-688.
I4 remains high a
is touched and is
also activates G4 which causes
to be generated. 1.9 mscc after
goes high, OACS
The trailing edge of OACS-P sets FF2 and
ensures FF3 is cleared. The
is inverted by inverter I3 cau
to go low, lighting the inh
e
output of FF2 is also Inverted by inverter
I5 causing MINH-N to go low, FF2 remains
set until an MRCU-N pulse is received or
another switch closure generates OACS-P.
5-692.  When the adh switch S6
touched, SADH-N goes low which acti-
vates G4. This causes SWIT-P to be
generated as explained previously.

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