PROGRAM MAINTENANCE PANEL INFIBUS ACCESS LOGIC CIRCUIT-CONT.

T.O.

31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

causing FNDS-P (waveform C, figure 109)

When a resister read switch closure is de-

to activate gate G19. The output of Gl9

tected, FRGS-P and SBCP-P go high which

s e t s F F 6 . T h e 0 output of FF6 disables

also activates G11, and DSCB-N, FMRA-N,

gates G14, G21, and G31 and activates

and FMRS-P are generated as explained.

When a step switch closure is detected,

gate G25 which ensures FF8 is cleared.

OAlG-N goes low when the second INFI-

If no other function is generating SELD-N,

BUS access is requested (reading data

gate G29 is enabled and the 1 output of

FF6 activates G29. The output of G29

from selected CPU register). OAlG-N sets

FF3 and DSCB-N, FMRA-N, and FMRS-P

sets FF11 which activates gate G20. The

are generated as explained. The 0 output

output of G20 presets flip-flop FF7, if it

of FF12 is also inverted by inverter I13.

is not already preset by a previous direct

The output of I13 enables gate G32 and

data transfer, and is coupled through

delay DL2 causes G32 to be activated 50

driver DR3 causing SRLD-N (waveform D,

nsec after it is enabled. The output of

figure 109) to go low. Presetting FF7 dis-

G32, STRF-N is coupled through driver

ables gate G14 and enables gates G17,

DR2 causing STRB-N (waveform H, figure

G 2 3 , a n d G 2 6 . In response to SRLD-N

109) to go low. Before STRB-N is gener-

the Bus Controller causes SELD-N (wave-

form E, figure 109) to go low and gener-

ated PCDA-P returns to low which disables

G33. This high output of G33 activates

ates the precedance pulse PCDA-P. When

G34 which clears FF11. Clearing FF11

SELD-N goes low, G29 is disabled, FF12

remains set, gate G30 is activated, and

disables G20 which causes SRLD-N to go

gate G33 is enabled. The low output of

high. The output of DR2, STRB-N, is also

G30 disables gate G28. When the prece-

coupled through inverter I4 which activates

gate G37. The output of G37 clears FF13

d a n c e p u l s e , PCDA-P (waveform F, figure

enabling G27, G29, and G38, disabling

109), is received, G33 is activated. The

G34 and G37, and causing SACK-N to go

output of G33 sets FF13 and disables gate

G 3 4 . The 0 output of FF13 disables gates

high.

G20, G22, G27, G.29, and G38 and. is

coupled through driver DR5 causing SACK-N

5-720. When the direct data transfer is

(waveform G, figure 109) to go low. The

completed the addressed function receiving

1 output of FF13 enabies G34 and activates

the data generates DONE-N. DONE-N is

gate G37 which sets FF12. The 1 output

inverted by inverter I6 causing DONF-P to

of FF12 is routed to gates G26, G27, G36,

go high which activates G27. The output

a n d G 3 8 . The 0 output of FF12, FOLR-N,

of G27, DONP-N, clears FF6 and is in-

disables G19, G21, and G29. The 0 out-

verted by inverter I12. The output of I12

put of FF12 is also coupled through inver-

activates gate G23 which presets FF9.

ter I3 causing AOUT-P to go high and it

FF9 remains set until the next OFDN-N

also activates gate G3 causing DOUT-P

pulse is received. DONP-N also acti-

to go high. AOUT-P strobes the address

v a t e s g a t e G 1 3 . The output of G13 is

to the INFIBUS address lines and DOUT-P

inverted by inverter I10 which clears FF3

strobes the data to the INFIBUS data lines.

a n d d i s a b l e s G 1 2 . The output of G13 also

AOUT-P also activates gate G1 because

a c t i v a t e s G 1 7 . The output of G17 acti-

FMRS-P is low except for address read,

vates G18 which resets FF5 causing FNDS-P

resister read, or step switch closures.

to go low which disables G19. Clearing

When an address read switch closure is

FF6 activates G24 and enables gate G31.

detected, FRDS-P and SBCP-P go high

The output of G24 ensures FF11 is cleared.

which activates gate G11. The output of

When DONE-N returns to high-, DONF-P

G11 sets FF3. The output of G13 activates

goes low and the output of G27 goes high

gate G12 causing DSCB-N to go low and is

activating G31 which clears FF12. The 0

output of FF12 is coupled through I13

inverted by inverter I9 causing FMRA-N

which disables G32 causing STRB-N to go

to go low. The output of FF3, FMRS-P,

high. Clearing FF12 also disables G26,

also disables G1 preventing RITE-N from

G27, G36 and G38.

going low during an address read operation.

5-113