PROGRAM MAINTENANCE PANEL INFIBUS ACCESS LOGIC CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-721. If DONE-N is not generated within

ables G28. When the precedence pulse,

2 usec after STRB-N is generated, the Bus

PCDA-P, is received G33 is activated

Controller generates QUIT-N. QUIT-N is

which sets FF13 and disables G34. The 0

inverted by inverters I16 and I17. The

output of FF13 disables G20, G22, G27,

output of I17 disables G37. The output of

G29, and G38 and is coupled through DR5

I16 activates G26 (FF11 still set). The

causing SACK-N to go low. The 1 output

output of G26 presets FF10 causing FATR-N

of FF13 enables G34 and activates G37

to go low. The output of I16 also activates

w h i c h ' s e t s F F 1 2 . The 1 output of FF11 is

G38 which sets FF14. The output of FF14

routed to G26, G27, G36, and G38. The

clears FF12 which disables G26. FF10

0 output of FF12, FOLR-N, disables G19,

remains set until the next OFDN-N pulse

G 2 1 , a n d G 2 9 . The 0 output of FF12, is

is received.

also coupled through I3 causing AOUT-P

to go high and it also activates G3 causing

5 - 7 2 2 , When the attn switch on the Pro-

DOUT-P to go high. AOUT-P now causes

gram Maintenance Panel miscellaneous

the Program Maintenance Panel address to

control circuit is touched, the Program

be strobed to the INFIBUS address lines and

Maintenance Panel INFIBUS access circuit

DOUT-P causes no data (zero address) to

causes a level 1 interrupt to be generated.

be strobed to the INFIBUS data lines. Be-

1.9 msec after the attn switch is touched

cause G11 is not activated, FF3 is not set

FTTR-N goes low and remains low for 24

and FMRS-P remains high which enables G1

causing RITE-N to go low when AOUT-P

msec after the attn switch is released.

A f t e r t h e r e l e a s e of t h e a t t n s w i t c h ,

goes high. RITE-N is also inverted by in-

OFDN-N goes low which clears FF9, FF10,

verter I1 which enables gate G6. The 0

and/or FF14, as necessary. For the fol-

output of FF12 also generates STRB-N, as

explained previously. Before STRB-N is

lowing discussion assume all flip-flops are

initially reset either by the completion of

generated PCDA-P returns to low which

a direct data transfer, the generation of a

d i s a b l e s G 3 3 . This high output of G33 acti-

previous level 1 interrupt, or receipt of a

vates G34 which clears FF11. Clearing

master reset pulse, MRES-N. FF4 sets on

FF11 disables G22 which causes SELl-N

t o g o h i g h . The output of DR2, STRB-N,

the trailing edge of FTTR-N. The output of

is also coupled through I4 activating G37.

FF4 is inverted by inverter I11, causing

The output of G36 clears FF13 which en-

FNlL-N to go low which causes the attn

ables G27, G29, and G38 and disables G34

LED (CR66) to light. The output of FF4

and G37, When STRB-N goes low, the ad-

also disables G15 causing RFl5-N to go

dress recognition signal SARP-P from the

high. RFlS-N being high disables G25 and

Program Maintenance Panel state genera-

FNlS-P activates gate G21 which sets FF8.

The 0 output of FF8 disables G19, G24,

tion and micro operations circuit goes high

and G31. The 1 output of FF8, FlSS-P,

which activates G6. When the attn switch

is touched OLTS-P goes high which disables

enables G22 and activates G29 if no other

gate G7. Theoutput of G6 activates gate

function is generating SELl-N. If another

G4 which triggers single shot SSl. The

function is generating SELl-N when SELl-N

output of SSl returns to high 100 nsec after

goes high, G29 is activated. The output of

it is triggered which presets flip-flop FF2.

G29 now sets FF11 and disables G30 and

Gate G8 is disabled by G7. The output of

G 3 3 . The output of FF11 enables G30 and

G33 and activates G22. The output of G22

FF2 activates gate G5. The output of G5

is coupled through DRl which generates

resets FF7, if it was preset, and is coupled

D O N E - N . The output of FF2 is also in-

through driver DR4 which generates SRLl-N.

verted by inverter I5. The output of I5 is

Resetting FF7 enables G14 and disables

delayed 50 nsec by delay DL2. After this

G17, G23, and G26. In response to SRLl-N

50 nsec delay, G5 is disabled which causes

the Bus Controller causes SELl-N to go low

DONE-N to go high. DONE-N is also in-

and generates the precedence pulse PCDA-P.

verted by I6 causing DONF-P to go high

When SELl-N goes low, G29 is disabled,

which activates G27 clearing FF8. DONP-N

FF11 remains set, G30 is activated and

a l s o a c t i v a t e s G 1 3 . The output of G13 is

G 3 3 i s e n a b l e d . The output of G30 dis-

5-114