PROGRAM MAINTENANCE PANEL ADDRESS MULTIPLEXER, BUS DRIVER RECEIVER, AND RECOGNITION CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

Program Maintenance Panel address/data

nition circuit. The CPU register selection

switch identification, multipiexers, and

circuit also displays the number of the CPU

LED circuit, the CPU register address in-

formation from the CPU register selection

circuit, or the CPU control register ad-

5 - 6 6 0 . Detail Analysis ( s e e f i g u r e 1 0 1 ) .

dress information to the INFIBUS address

Initially, MRE-N from the Program Mainte-

l i n e s . The address multiplexer, bus driver

nance Panel address/data switch identifi-

receiver, and recognition circuit also

c a t i o n multiplexer, and LED circuit resets

notifies the Program Maintenance Panel

the CPU selection storage register U62.

state generation and micro operations

When register 15 switch (S2) is touched,

circuits when the address on the INFIBUS

RS15-P goes high and is routed to the

equals the address selected by the Program

decimal-to-BCD encoder U52. When

Maintenance Panel address/data switch

RS15-P goes high the four outputs (01

identification, multiplexers, and LED

through 04) and the STRB output of

circuit. These circuits also indicate when

decimal-to-BCD encoder U52 goes low

the INFIBUS is busy and notify the Program

generating RGSL-N which is routed to the

Maintenance Panel state generation and

Program Maintenance Panel address/data

micro operations circuit when the Program

switch identification, multiplexers, and

Maintenance Panel address is on the

LED circuit. Inverter I2 enables gate Gl

INFIBUS address lines.

and RGSL-N is inverted by inverter I1, also

enabling Gl. 1.9 msec after RGSL-N goes

5 - 6 6 3 . Detail Analysis (see figure 102).

low, OACS-P from the Program Maintenance

When ARAB-P and CRAB-N are high (ad-

Panel address/data switch identification,

dress register selection), gates G2, G3,

multiplexers, and LED circuit is generated

G4 and G5 are enabled and AOOS-P through

for 3.4 msec which activates Gl. The

delayed 3.4 msec pulse out of Gl clocks

A15S-P are coupled through the address

the four high outputs (01 through 04) of

multiplexers U46, U56, U66 and U76.

decimal-to-BCD encoder U52 into CPU

When AOUT-P goes high the inputs are

selection register U62. The four outputs

strobed through address bus driver re-

(RAO1-N through RA04-N) of CPU selection

ceivers U50, U60, U70 and U80. The

information on the INFIBUS, ABOO-N through

Maintenance Panel address multiplexers,

AB15-N, either from the INFIBUS or address

bus driver receiver, and recognition circuit.

bus driver receivers U50, U60, U70, and

The other four outputs, QAl through QDl,

U80 is coupled through address bus driver

of CPU selection register U62 are routed to

receivers U50, U60, U70, and U80 to the

the BCD-to-decimal decoder U72, generating

address exclusive-nor gates U47, U57,

R15L-N which lights the reqister 15 LED

U67, and U77. If AOOS-P through Al5S-P

(CR2). If two register switches are touched

equals AOOA-P through Al5A-P, the output

simultaneously, the KRO output of the

of address exclusive-nor gates U47, U57,

decimal-to-BCD encoder U52 goes low

U67 and U77 is high. If address bit 15

which disables Gl. Disabling G1 prevents

(A15S-P) in the address shift register of

the 01 through 04 outputs of decimal-to-

the Program Maintenance Panel address/

BCD encoder U52 from being clocked into

data switch identification, multiplexers,

CPU selection register U62.

and LED circuit is high, the output of

the address multiplexer U46 is low,

5-661.

PROGRAM MAINTENANCE PANEL

enabling gate Gl. When AOUT-P goes

ADDRESS MULTIPLEXER, BUS

high, Gl is activated and ABl5-N

DRIVER RECEIVER, AND RECOG-

goes low. ABl5S-N is inverted by

NITION CIRCUIT.

inverter I1 (Al5A-P goes hiqh). With

A15A-P and A15S-P both high, the output

5 - 6 6 2 . General.

The Program Maintenance

of gate G6 is high, enabling gate G7.

Panel address multiplexer, bus driver

STRB-N is inverted by inverter 12 and gate

receiver, and recognition circuit strobes

G7 is activated 50 msec after STRB-N goes

either the address information from the

low by the delay of DLl, causing EQA4-P

5-101