PROGRAM MAINTENANCE PANEL DATA MULTIPLEXER AND BUS DRIVER RECEIVER CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

to go high. The output of I2 is also routed

INFIBUS address lines. HCYC-N is high

to SS1. As long as SS1 is being triggered

which is inverted by inverter I9, which

at least once every 0.088 sec, its output

activates gate G14. PBOO-N and PB0l-N

remains high. This high level output of

are always low, and if Al5A-P through

SSl is inverted by inverter I3, which

A07A-P are high, and A06A-P through

causes the busy LED (CR39) to light. When

A02A-P are low, the junction of the outputs

STRB-N remains high for longer than 0.088

of G9, G10, G11, G12, G13, G14, I5, I6,

sec the output of SSl returns to a low level

I7 and I8 remains low until the output of I2

and the busy LED goes out.

goes high. Delay DL2 delays the positive

going edge of the output of G8, G9, G10,

5 - 6 6 4 . When ARAB-P is low and CRAB-N

G11, G12, G13, G14, I5, I6, I7 and I8 to

is high (CPU register selection), the 0

prevent false address recognition. The

volt, +5 volts, CPUO-N and CPUl-N (both

output of DL2 is inverted by inverter I4.

high) and RAl-N through RAl-N inputs are

This causes SARO-N to go low which

coupled through address multiplexer U46,

notifies the Program Maintenance Panel

U56, U66, and U76. G2, G3, G4, and G5

state generation and micro operations

are enabled by CRAB-N being high and the

circuit that address recognition has

outputs of address multiplexer U46, U56,

occurred.

U66, and U76 and G2, G3, G4, and G5

are strobed through bus driver receivers

5-667. PROGRAM MAINTENANCE PANEL

DATA MULTIPLEXER AND BUS

U50, U60, U70, and U80 when AOUT-P

goes high. For this condition AB15-N

DRIVER RECEIVER CIRCUIT.

through AB08-N are low, AB07-N, AB06-N,

AB05-N, and ABOO-N are high, and the

5 - 6 6 8 . General. The Program Maintenance

Panel data multiplexer and bus driver re-

selected CPU register address is

ceiver circuit can couple the address or

/l,l,l,l,/l,l,l,l,/0,0,0, RAO4-N,/

RA03-N, RA02-N, RA0l-N, O/. A15A-P

data information from the Program Main-

tenance Panel address/data switch identi-

through AOOS-P now does not equal A15S-P

fication, multiplexer, and LED circuit to

through AOOS-P and the output of the ex-

the INFIBUS and couple data information

clusive-nor gates U47, U57, U67, and

U77 is not high and EQA4-P is not

from the INFIBUS to the address/data

generated.

switch identification, multiplexer, and

LED circuit. The Program Maintenance

5 - 6 6 5 . When ARAB-P and CRAB-N are low

Panel data multiplexer and bus driver

receiver circuit can also couple either the

(CPU control register selection) the 0 volt,

halt command, run command, step command,

+5 volts, CPUO-N and CPUl-N (both high)

and the RA04-N through RAOl-N inputs are

zero address, or Program Maintenance

coupled through address multiplexer U46,

Panel address to the INFIBUS.

U56, U66 and U76. G2, G3, G4, and G5

are disabled (output low) by CRAB-N being

5 - 6 6 9 . Detail Analysis (see figure 103).

low and the outputs of address multiplexer

The address shift register outputs, AOOS-P

U46, U56, U66, and U76 and G2, G3, G4,

through A15S-P, from the Program Mainte-

and G5 are strobed through bus driver

nance Panel address/data switch identifi-

receivers U50, U60, U70 and U80 when

cation, multiplexer, and LED circuits are

AOUT-P goes high. EQA4-P is not gener-

coupled through the data multiplexers U6,

ated, as explained previously.

U16, U26 and U36 when DRDB-N is high

and RNDB-P, VADB-P, and HTDB-P are low.

5-666. When the Program Maintenance

When VADB-P is low, gates G2 through G10

Panel is operating in the slave mode (being

are enabled. When RNDB-P and HTDB-P

addressed by another module), gates G8,

arc low gates G13 and G14 are enabled.

G9, G10, G11, G12, G13, and G14 and

With both RNDB-P and VADP-B low, gate

inverters I6, I7, and I8 determine when the

G15 is disabled (output high). The low

Program Maintenance Panel address, FF8X

level of HDTB-P is inverted by inverter I7.

The high outputs of gate G15 and inverter

(/1111/1111/1000/01XX/), is on the

5-102