PROGRAM MAINTENANCE PANEL CPU REGISTER SELECTION CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

driver receiver circuit. The 16-bit paral-

count 16, S MUX-P goes high which acti-

lel address information is clocked into

vates G21. The output of G21 is inverted

address shift registers U58 and U78 by

by Ill which activates G24. DSCA-N is

ASCA-N which at this time is the ASCB-N

now at the sixteenth pulse and the data 15

signal from the Program Maintenance Panel

information is stored in data shift registers

INFIBUS access circuits.

U8 and U28. Al5S-P goes high, and is

inverted by inverter I14 which causes the

5-656. If a data switch was touched,

data 15 LED (CR44) to light. For each

ODAS-P enables and G21. G8 is acti-

additional data switch closure the above

vated 1.9 msec after ODAS-P is generated,

sequence is repeated and the data informa-

as explained previously. The output of G8

tion stored in data shift registers U8 and

(waveform C, figure 100) is applied to

U28 is circulated back to its original posi-

flip-flop FF2. FF2 is set on the next nega-

tion by G24. If the data clear switch (S55)

tive going edge of the clock output of I6.

is touched, the data clear LED (CR56)

The 1 output of FF2 is inverted by inverter

lights and G25 is activated which resets

I2. The output of I2 is applied to DLl

data shift registers U8 and U28. If a data

which delays the positive going edge of

switch is touched a second time, the asso-

FSDA-N only. The output of DLl, FSDA-N

ciated bit position in data shift registers

(waveform E, figure 100), enables data

U8 and U28 are cleared. If data 15 switch

is touched a second time, the above se--

shift registers U8 and U28 to shift data

quence is repeated except at the sixteenth

information serially left (D15S-P to DS-P)

DSCA-N clock pulse DOOS-P and DMUX-P

when triggered by DSCA-N. The 1 output

are both high. The output of G24 is low

of FF2 enables gate G9 to couple the clock

and a 0 is clocked into bit position 15 of

output of I6 to G10 and data shift registers

data shift registers U8 and U58 which

U8 and U28. The 0 output of FF2 enables

causes the data 15 LED to go out.

shift counter U12. The gated clock pulses

out of G9 (waveform F, figure 100) are

5-657. When 7ACT-P from the Program

coupled through G10 to trigger shift counter

Maintenance Panel switch flip-flops and

U12. When shift counter U12 reaches the

single action discriminator circuit is

sixteenth count, G16 is activated. The

output of G16 is inverted by I8 and applied

generated, it is inverted by inverter I1

which activates G5. The output of G5 acti-

to the clear input of FF2. The next trailing

edge of the clock output of I6, clears FF2

vates G6 which causes OACS-P and OLTS-P

to be generated, as explained previously.

which clears shift counter U12 and disables

If RGSL-N goes low, G5 is activated which

G9 causing FSDA-N to go high. The shift

causes OACS-P and OLTS-P to be generated.

counter U12 generates BCD signals SClS-P,

SC2S-P, SC4S-P, and SC8S-P which are

If SWIT-P from the Program Maintenance

Panel miscellaneous control circuit goes

routed to address/data bit multiplexer U50.

Address/data bit multiplexer US 0 converts

high, G6 is activated and OACS-P and

e parallel inputs (only one low) to a

OLTS-P are generated, as explained previ-

serial output as strobed by the outputs of

ously. However, because OADS-P and

shift counter U12 for each -

data switch

ODAS-P are low shift counter U12 and ad-

closure. This serial data, SMUX-P,

dress shift registers U58 and U78 or data

activates gate G21. The output of G21 is

shift registers U8 and U28 are not enabled.

inverted by I11. The output of Ill, DMUX-P,

5-658. PROGRAM

INTENANCE PANEL

is routed to gate G24. The 16 DSCA-N

CPU REGISTER SELECTION CIRCUIT.

pulses cl

the serial data information

bits, DM

P, into data shift registers

5-659. General. `The Program Maintenance

U8 and U28 for each data switch closure.

Panel CPU register selection circuit con-

The first data switch closure clocks the

verts the CPU register selection switch

data information into the proper position

closure to a 4-bit BCD signal that is routed

of data registers U8 and U28. If data 15

to the Program Maintenance Panel address

switch is touched first, SMUX-P remains

multiplexer, bus driver receiver, and recog-

low until the shift counter U12 reaches

5-100