PROGRAM MAINTENANCE PANEL ADDRESS/DATA SWITCH IDENTIFICATION, MULTIPLEXERS, AND LED CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

G12 which disables G18. The output of

above sequence is repeated and the ad-

G18 disables G19 which causes INAX-P

dress information stored in address shift

to go low. The information remaining in

registers U58 and U78 is circulated back

the address shift register is circulated,

to its original position through G22. If

as explained previously, by the ASCA-N

the address clear switch (S37) is touched,

pulses until shift counter U12 reaches a

the address clear LED (CR37) lights and

count of 16. When a count of 16 is

SCLA-N activates G23 which resets ad-

reached, G13 is activated. The output of

dress shift registers U58 and U78. If an

G13 is inverted by I8 which resets FF3

address switch is touched a second time,

and FF4. Resetting FF3 and FF4 clears

the associated bit position in address

shift counter U12 and disables address

shift registers U58 and U78 is cleared. If

shift registers U58 and U78.

the address 15 switch is touched a second

time, the above sequence is repeated

5 - 6 5 4 . To increment address shift regis-

except; at the sixteenth ASCA-N clock

ters U58 and U78 by two is similar to in-

pulse AOOS-P and INAX-P are both high.

crementing the address shift register by

The output of G22 is low and a 0 is clocked

one, except BYSW-N is high. BYSW-N

into bit position 15 of address shift regis-

is inverted by I9 which disables G15 and

ters U58 and U78 which causes the address

G18 and enables G17. The output of G14

15 SLED to go out.

is high at a count of 0 which disables G17.

The output of G14 is also inverted by

5-653. To increment address shift regis-

inverter I/O which disables G5. After the

ters U58 and U78 by one, FF3 is preset by

first count, the output of G14 goes low

FSAT-N from the Program Maintenance

activating G18 and is inverted by I10

Panel state generation and micro operations

which enables G15. Activating G18 acti-

circuit and lPNC-N presets FF5. Setting

vates Cl7 causing INAX-P to go high for

FF3 sets FF4 on the next trailing edge of

the second and following counts. When

the clock pulse out of I6. Setting FF4 en-

INAX-P and AOOS-P are high, G22 functions

ables shift counter U12 and address regis-

as a half adder and a 0 is clocked into

ters U58 and U78, as explained previously.

the associated position of address shift

The shift counter generates the BCD signals

registers U58 and U78 where a 1 was stored.

SC15-P, SC2S-P, SC4S-P, and SC8S-P and

INAX-P remains high until AROO-N goes

the 16 ASCA-N pulses, as explained previ-

high which corresponds to a 0 in associated

ously. BYSW-N is low when address shift

address shift registers U58 and U78 bit

registers U58 and U78 are to be incremented

position. When AROO-N goes high, G15

by one. BYSW-N is inverted by I9 which

is activated which activates G16. On the

enables G25 and G17. The 1 output of FF5

next negative going edge of the clock

activates G17 which activates G20 holding

pulse out of G12, a 1 is clocked into ad-

INAX-P high. When INAX-P and AOOS-P

dress shift registers U58 and U78 because

are high, G22 functions as a half adder

and a 0 is clocked into the associated bit

INAX-P is still high. This increments ad-

position of address shift registers U58 and

dress shift registers U58 and U78 by two

U78 where a 1 was stored. INAX-P re-

because the 0 bit position of the address

mains high until AROO-N goes high, which

shift register was skipped by the action of

corresponds to a 0 in associated address

G14. The remaining address shift regis-

shift registers U58 and U78 bit position.

ters U58 and U78 information is circulated,

When AROO-N goes high G15 is activated

the shift counter U12 is cleared and the

which activates G16. On the next negative

address shift register is disabled as ex-

going edge of the clock pulse out of G12,

plained previously.

a 1 is clocked into address shift registers

U58 and U78. This occurs because INAX-P

5 - 6 5 5 . When PSAA-N is high address shift

is still high, incrementing the address in

registers U58 and U78 can accept the

address shift registers U58 and U78 by

16-bit parallel address information DOOA-P

one. FF5 is cleared on the second nega-

through D15A-5 from the Program Mainte-

tive going edge of the clock pulse out of

nance Panel data multiplexer and bus

5-99