PROGRAM MAINTENANCE PANEL ADDRESS/DATA SWITCH IDENTIFICATION, MULTIPLEXERS, AND LED CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

to to high which prevents a data switch

output of I6 to inverter I5 and FF5.

closure from being sensed during the time

The I output of FF4 is coupled through

OADS-P is high. A data switch closure

inverter I7 and delay DL2. DL2 delays

operates similarly to an address switch

the positive going edge of FSAA-N

closure, except SS2 is triggered and the

only. The output of DL2, FSAA-N

output of gate G3 is high for the duration

(waveform E, figure 100), enables

of ODAS-P. This prevents an address

address shift registers U58 and U78 to

switch closure from being sensed during

shift address information serially left

the time ODAS-P is high. When FBAS-P

(A15S-P to AOOS-P) when triggered by

from the Program Maintenance Panel switch

ASCA-N. The 0 output of FF4 enables the

flip-flops and single action discriminator

shift counter U12 to count. The gated

circuit is generated, Gl and G2 are acti-

clock pulses out of G12 (waveform F,

vated which holds SSl and SS2 cleared

figure 100) are inverted by I5 and activate

preventing either an address or data switch

gate G10 which triggers the shift counter

closure from being sensed.

U12. When shift counter U12 reaches the

sixteenth count, G13 is activated. The

5 - 6 5 1 . Initially, MRES-N is inverted by

output of G13 is inverted by inverter 18

I3 and I4. The output of I4, MREW-N,

and applied to the clear input of FF4. The

resets flip-flops FF2, FF3, and FF4 and

next trailing edge of the clock output of

single shot SS5. Resetting SS5 causes

I6 clears FF4 which clears shift counter

U12 and disables G12. Disabling G12

OLTS-P to hold flip-flop FFl reset.

causes FSAA-N to go high. The shift

MREW-N activates G23 and G25 which

counter U12 generates BCD signals SC IS-P,

resets address shift registers U58 and U78

and data shift registers U8 and U28. When

SC2S-P, SC4S-P, and SC8S-P which are

routed to the address/data bit multiplexer

O-ADS-P or ODAS-P goes high and if 7ACT-P

and SWIT-P are low and RGSL-N is high,

U50. Address/data bit multiplexer U50

converts the parallel inputs (only one

the output of gate G6 (waveform A, figure

input low) to a serial output. SCSl-P,

100) goes low triggering single shot SS3.

SCS2-P, SCS4-P, and SCS8-P sequentially

At the same time single shot SS5 is en-

enables the EO through El5 inputs to the

abled to be triggered by the output of in-

verter I6. I6 inverts CLKI-N from the

address/data bit multiplexer to be coupled

to the output X as SMUX-P. This serial

Program Maintenance Panel state genera-

data, SMUX-P, activates G20 which acti-

tion and micro operations circuit. The

vates gate G19. The output of G19,

output of I6 retriggers SS5 every 640 nsec.

INAX-P, is routed to gate G22. The 16

This causes OLTS-P to go high, enabling

ASCA-N pulses clock the serial address

FFl to be set. The output of SS3 (wave-

information bits, INAX-P, into address

form B, figure 100) returns to a high 1.9

shift registers U58 and U78 for each

msec after OADS-P or ODAS-P goes high,

triggering single shot SS4 which generates

address switch closure. The first address

switch closure clocks the address informa-

OACS-P (waveform C, figure 100). The

tion into the proper position of address

trailing edge of the low output of SS4 sets

registers U58 and U78. Assume address 15

FFl which holds SS3 and SS4 cleared.

switch is touched first, SMUX-P remains

OLTS-P (waveform D, figure 100) goes low

low until the shift counter U12 reaches

24 msec after the output of G6 returns to

count 16, SMUX-P then goes high. SMUX-P

high. When OLTS-P goes low FFl is reset

is coupled through G20, G19, and G22 to

enabling SS3 and SS4 for the next switch

closure.

the shift left input of address shift register

U58 and U78. ASCA-N is now at the

5 - 6 5 2 . If an address switch was touched,

sixteenth count and the address 15 inform-

ation is stored in address shift registers

OADS-P enables gates G7 and G20.

U58 and U78. A15S-P goes high, is

The output of G7 activates G11. FF4 IS

inverted by inverter I12 and causes the

set on the next negative going edge of the

address 15 LED (CR21) to light. For each

clock output of I6. The i output of FF4

additional address switch closure the

enables gate GI2 to couple the clock

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