PROGRAM MAINTENANCE PANEL ADDRESS/DATA SWITCH IDENTIFICATION, MULTIPLEXERS, AND LED CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

FF11 disables G29 and resetting FF12 dis-

functions are not requesting a direct

CCL

ables Gl which disables G4, G6, G8, G10,

memory access, shift register U4 continues

and G12.

to serially shift data, as explained previously

PROGRAM MAINTENANCE PANEL

5-648.

5-645. When the CCL function is re-

ADDRESS/DATA SWITCH IDENTI-

questing a level 2 interrupt INFIBUS access,

FICATION, MULTIPLEXERS, AND

operation is similar to when the RSJ is

LED CIRCUIT.

requesting a level 2 interrupt INFIBUS ac-

cess except CCL INT REQ is high. This

5 - 6 4 9 . General. The Program Maintenance

causes the same operations as when RSJ

Panel address/data switch identification,

INT REQ was high, except G9 is enabled

multiplexers, and LED circuit provides

by the output of register U15 and activated

identification of any address or data switch

when OD-N is low. Activating G9 causes

closure. It generates 16 shift pulses for

shift register U4 to stop serially shifting

serially loading either the address or data

data when OD-N is low. When FF2 is set

G10 is activated which causes CCL INT

shift registers with the latest address or

ACK to go high. Also, the output of G9,

data information as determined by the ad-

dress or data switch closures. It contains

R4-N, activates G16 which causes a re-

circuits to display either the address and

quest for a level 2 interrupt INFIBUS ac-

data information as determined by the ad-

cess to be generated, as explained pre-

dress or data switch closures or the ad-

viously.

dress and data information from the data

multiplexer and bus driver receiver circuit.

5-646. When the RMR function is re-

The Program Maintenance Panel address/

questing a level 2 interrupt INFIBUS ac-

data switch identification, multiplexers,

cess, operation is similar to when the RSJ

is requesting a level 2 interrupt INFIBUS

and LED circuits also provides circuits

For serially incrementing the address shift

access except RMR INT REQ is high. This

causes the same operations as when RSJ

names indicate front panel placarded

INT REQ was high, except G11 is enabled

nomenclature.

by the output of register U15 and activated

when OE-N is low. Activating G11 causes

5-650. Detail Analysis (see figure 99).

the shift register U4 to stop serially

When OADS-P and ODAS-P are low and

shifting data when OE-N is low. When

ENBL-N is low, both gates G3 and G4 are

FF2 is set, G12 is activated which causes

able to sink current through inductors

RMR INT ACK to go high. Also, the output

Ll and L2, respectively, if an address or

of G11, R5-N activates G16 which causes

data switch is closed. When the address

a request for a level 2 interrupt INFIBUS

15 switch (S21) is touched, current begins

access to be generated, as explained

to flow from the output of G3, through L2,

previously.

S21, and resistor R8. ENAD-N rises in-

stantly to 5 volts and then decays to 0

5-647. If in the RSJ or CCL direct memory

access operation or the RSJ, CCL, or RMR

volts in less than one msec. This positive

level 2 interrupt INFIBUS access operation

differentiated voltage spike is coupled

the I/O Controller INFIBUS access logic

through driver DR2, differentiator L3 and

circuit does not receive DONE-P within

R16, to trigger single shot SSl on its

2 USeC after STRB-N is generated, the Bus

leading edge. The double differentiation

Controller generates QUIT-N. QUIT-N is

is necessary to prevent oscillations be-

inverted by inverter I23 which activates

tween SSl and single shot SS2 after SSl

G28. Activating G28 generates i/O QUIT

or SS2 is triggered. When SS1 is triggered,

for the duration of QUIT-N. The output of

OADS-P is generated for 3.55 msec.

I23, QUIT-P, activates G33 (STRB ENBL-N

OADS-P causes the output of gate G2 to go

low) which resets FF9, FF11, and FF12.

low, forcing SS2 to remain cleared.

Resetting FF9 removes STRB-N. Resetting

OADS-P also causes the output of gate G4

5-97