I/O CONTROLLER INFIBUS ACCESS LOGIC CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

ables the S input of shift register U4. Dis-

125 nsec after it was triggered which

abling the S input of shift register U4 pre-

triggers and sets FF11. The output of

vents the shift register U4 from serial

FF11 activates G29 (STRB-N high) which

shifting the data which causes OC-N to

triggers SS1 and sets FF12. The 0 output

remain low for as long as G7 is activated.

of FF12, RDY NXT CYCLE-N, activates Gl

The high output of G13 disables G2 which

which activates G8. G8 generates RSJ

allows FF2 to be set when triggered, The

INT ACK which notifies the RSJ function

high output of G13 is also inverted by I3

that the level 2 interrupt request has

causing SERV REQ-N to go low. SERV

been acknowledged. The 1 output of

REQ-N is inverted by I22 which enables

FF12, RDY NXT CYCLE-P, enables FFl to

FF8 to be set, is inverted by I21 which

be set. 125 nsec after SS1 is triggered,

enables FF4, FF5, and FF7 to be set, and

the output of SS1 sets FF9. The 0 output

activates G31. The output of G31,

of FF9 is coupled through bus driver/

BUSEN-P, enables bus driver/receivers

receivers U38 which generates STRB-N

U38 and bus drivers U51. The output of

and STRB-P. STRB-P is inverted by I25

G16, INT REQ (waveform K, figure 98), is

which disables G29. STRB-P is high

inverted by I16. The output of I16 is in-

which enables gate G27. The 1 output of

FF9, STRB INT-P, activates G27 which

verted by I18 which enables FF6 to be set.

If no other function is requesting a level

resets FF4, FF5, and FF7. Resetting FF7

2 interrupt INFIBUS request, SEL2-N is

causes SACK-N to return to a high level

high which is inverted by inverter I19.

and resetting FF4 and FF5 enables G21 to

The output of I19 disables gate G23 and

couple PCDA-P to the INFIBUS as PCDB-P.

When the level 2 interrupt is complete,

is inverted by inverter I20. The output

the CPU generates DONE-N which causes

of I20 enables gate G22. The output of

the I/O Controller address recognition,

I16 is also delayed 50 nsec by DL2 and

done, and reset circuit to generate DONE-P.

then inverted by inverter I17. The output

DONE-P is inverted by inverter I1. The

of I17 activates G22 which sets FF6. The

trailing edge of the output I1 (trailing

1 output of FF6 enables G23 and the 0 out-

put of FF6 is coupled through bus drivers

edge of DONE-P) sets FFl which activates

U51 which generates SRL2-N. In response

G 2 . The output of G2 resets FF2 which dis-

to SRL2-N the Bus Controller causes SEL2-N

a b l e s Gl. Disabling Gl causes RSJ INT

to go low which is inverted by I19 and I20.

ACK to go low which causes RSJ INT REQ to

The output of I20 disables G22 and the out-

go low. The positive going edge of Q2-N

put of I19 activates G23 which sets FF5 and

after RSJ INT REQ returns to low causes the

enables gates G24 and G26. The 0 output

Q3 output of register U15 to return to a low

of FF5 disables G21 preventing the pre-

level which disables G7. The output of G7,

cedance pulse, PCDA-P, (when received)

R3-N, now goes high disabling G13 which

enables shift register U4 to serially shift

from being coupled through G21. When

data, on the second negative going edge of

PCDA-P is received, G26 is activated which

sets FF7 and FF8 and activates G24. The

Q2-`P (due to internal delays of register

output of G24 resets FF6 which disables

U15, G2, G13, and G14), as explained

G23. The output of G23 disables G24 after

previously. R3-N also disables G16 which

FF6 has reset. The 0 output of FF7 is

causes INT REQ-P to go low which holds

coupled through bus drivers U51 to the

FF6 reset. The low output of G13 is a also

inverted by I3 which causes SERV REQ-N to

FIBUS as SACK-N. The 0 output of FF8

disables G18 and gate G22. The 1 output

When SERV REQ-N goes high FF4

go high.

of FF8, SELECT-P, enables gate G28,

FF5, FF7, FF8, and FF10 are reset. Re-

setting FF2 causes STRB ENBL-N to go high

sets FF2, and triggers single shot SS2.

which activates G33. The output of G33

Setting FF2 enables G1 and generates

resets FF9, TF11, and FF12. If the CCL and:

STRB ENBL-N. STRB ENBL-N disables G33

which allows flip-flops FF9, FF11, and

RMR functions arc not requesting a level 2

FF12 to be set when triggered. SS2 resets

interrupt INFIBUS access, and if the RSJ and

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