I/O CONTROLLER INFIBUS ACCESS LOGIC CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

return to a low level which disables G3.

G19. The output of G19 disables G20 after

The output of G3, Rl-N, now goes high

FF3 has reset. The 0 output of FF7 is

disabling G13 which enables the shift

coupled through bus drivers U51 to the INFI-

BUS as SACK-N. The 0 output of FF8 disables

second negative going edge of Q2-P (due

gates G18 and G22. The 1 output of FF8,

to internal delays of register U15, G2,

SELECT-P, enables gate G28, sets FF2, and

G13, and G14), as explained previously.

triggers single shot SS2. Setting FF2 en-

Rl-N also disables G15 causing DMA

ables gate Gl and generates STRB ENBL-N.

REQ-P to go low which holds FF3 reset.

STRB ENBL-N disables G33 which allows

The low output of G13 is also inverted by

flip-flops FF9, FF11, and FF12 to be set

I3 which causes SERV REQ-N to go high.

when triggered. SS2 resets 125 nsec after

When SERV REQ-N goes high FF4, FF5, FF7,

it was triggered which triggers and sets

FF8, and FF10 are reset and the bus driver

F F l l . The output of FFll activates gate

receiver are disabled. Resetting FF2

G29 (STRB-N high) which triggers SSl and

causes STRB ENBL-N to go high which acti-

sets FF12. The 0 output of FF12, RDY

vates G33. The output of G33 resets FF9,

NXT CYCLE-N, activates Gl which acti-

FF11, and FF12. If the CCL function is not

vates G4. G4 generates RSJ DMA ACK

requesting a direct memory access and if

which notifies the RSJ function that the

the RSJ, CCL, and RMR functions are not

direct data transfer request has been

requesting a level 2 interrupt INFIBUS ac-

acknowledged. If the RSJ function is re-

c e s s , shift register U4 continues to ser-

questing a write operation, RSJ WRITE is

ially shift data as explained previously.

high which enables gate G34. Rl-N is in-

verted by inverter I26 which activates G34.

5 - 6 4 3 . When the CCL function is requesting

The output of G34 enables G32. The 1 out-

a direct memory access, operation is similar

put of FF12, RDY NXT CYCLE-P, enables

to when the RSJ function is requesting a

FFl to be set and activates G32. The out-

put of G32 is coupled through bus driver/

direct memory access except CCL DMA

receivers U38 generating RITE-N and en-

REQ is high. This causes the same opera-

abling FF10 to be set. 125 nsec after SSl

tions as when RSJ DMA REQ was high,

is triggered, the output of SSl sets FF9.

except G5 is enabled by the output of

The 0 output of FF9 is coupled through bus

driver/receivers U38 which generates

low. Activating G5 causes the shift regis-

STRB-N and STRB-P. STRB-P is inverted

ter to stop serially shifting data when OB-N

by inverter I25 which disables G29. STRB-P

is low. When FF2 is set, G6 is activated

is high which enables gate G27. The 1 out-

which causes CCL DMA ACK to go high.

put of FF9, STRB INT-P, activates G27

Also, the output of G5 (R2-N) activates

which resets FF4, FF5, and FF7. Resetting

G15 which causes a request for a direct

FF7 causes SACK-N to return to a high

data transfer to be generated, as explained

level and resetting FF4 and FF5 enables

previously. If the CCL function is re-

G21 to couple PCDA-P to the INFIBUS as

questing a write operation, CCL WRITE is

PCDB-P. When the DDT is complete, the

high which enables G34. When R2-N goes

function addressed by the RSJ function

low and is inverted by inverter I27, G34

generates DONE-N which causes the I/O

is activated which causes RITE-N to be

Controller address recognition, done and

generated, as explained previously.

reset circuit to generate DONE-P. DONE-P

5 - 6 4 4 . When the RSJ function is requesting

is inverted by inverter Il. The trailing

edge of the output of I1 (trailing edge of

a level 2 interrupt INFIBUS access, RSJ INT

DONE-P) sets FF1 which activates G2.

REQ (waveform J, figure 98) goes high.

The output of G2 resets FF2 which dis-

The trailing edge of Q2-N clocks the high

a b l e s Gl. Disabling Gl causes RSJ DMA

level of RSJ INT REQ into shift register U15

ACK to go to low which causes RSJ DMA

which enables G7. G7 is activated when

REQ to go low. The positive going edge of

OC-N goes low. The output of G7, R3-N,

Q2-N after RSJ DMA REQ) returns to low

enables G8 and activates G13 and G16.

causes the Ql output of register U15 to

The output of G13 activates G14 which dis-

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