I/O CONTROLLER INFIBUS ACCESS LOGIC CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM ll-5805-663-14-13

NAVELEX 0967-464-0010

which resets flip-flop FF2. Resetting FF2

an RSJ DMA REQ, CCL DMA REQ, RSJ INT

disables gates G4, G6, G8, G10, and G12

REQ, CCL INT REQ, or RMR INT REQ input

and STRB ENBL-N (high) activates G33

is detected.

which resets flip-flops FF9, FF11, and

FF12. T h e l o w o u t p u t o f G 1 3 i s a l s o i n -

5-642. When the RSJ function is requesting

verted by inverter I3 which causes SERV

a direct memory access, RSJ DMA REQ

R E Q - N t o g o h i g h . SERV REQ-N is inverted

(waveform H, figure 99) goes high. The

by inverter I22 which resets flip-flop FF8,

trailing edge of Q2-N clocks the high level

and by inverter I21 which resets flip-flops

of RSJ DMA REQ into register U15 which

FF4; FF5, and FF7. Resetting FF8 causes

enables G3. G3 is activated when OA-N

SELECT-P to go low which resets FFl.

goes low. The output of G3, Rl-N, enables

With FF4 and FF5 reset, gate G21 is enabled

G4 and activates G13 and G15. The output

to couple the precedance pulse, PCDA-P,

of G13 activates G14 which disables the

from the INFIBUS to the INFIBUS as PCDB-P.

S input of shift register U4. Disabling the

S input of shift register U4 prevents the

5-641. With the L input of shift register

shift register from serial shifting the data

U4 enabled and the S input disabled, the

which causes OA-N to remain low for as

first trailing edge of Q2-P (waveform A,

long as Gl is activated. The high output

figure 90) triggers shift register U4 which

of G13 disables G2 which allows FF2 to be

parallel loads shift register U4. Parallel

set when triggered. The high output of

loading of shift register U4 causes OA-N

G13 is also inverted by I3 causing SERV

(waveform C, figure 98) OB-N (waveform D,

R E Q - N t o g o l o w . SERV REQ-N is inverted

figure 98), OC-N (waveform E, figure 98),

by I22 which enables FF8 to be set. SERV

and OD-N (waveform F, figure 98) to go

REQ-N is also inverted by I21 which enables

high which activates gate G17 causing OE-N

FF4, FF5, and FF7 to be set and activates

(waveform G, figure 98) to go low. When

gate G31. The output of G31, BUSEN-P,

GEN RESET-N returns to high, which is in-

enables bus driver/receivers U38 (G30

verted by I5, G14 is disabled and the L

shown) and bus drivers U51 (G25 shown).

input of shift register U4 is also disabled.

The output of G15, DMA REQ (waveform I,

If RSJ DMA REQ, CCL DMA REQ, RSJ INT

figure 98), is inverted by I11. The output

of I11 is inverted by I13 which enables FF3

REQ, CCL INT REQ, and RMR INT REQ are

all low, the outputs of register U15 all re-

t o b e s e t . If no other function is requesting

a direct data transfer INFIBUS request,

main low holding G3, G5, G7, G9, and

SELD-N is high which is inverted by inver-

G11 disabled which holds G13 disabled.

ter I14. The output of I14 disables gate

The low outputs of G13 and I5 disable G14.

G19 and is inverted by inverter I15. The

The high output of G14 enables the S input

output of I15 enables gate G18. The output

o f s h i f t r e g i s t e r U 4. The serial input (SA)

of Ill is also delayed 50 nsec by DLl and

of shift register U4 at this time is low.

then inverted by inverter I12. The output

Under these conditions, the first trailing

of I12 activates G18 which sets FF3. The

edge of Q2-P, after GEN RESET-N goes

1 output of FF3 enables G19 and the 0 out-

high, causes OA-N to go low which disables

put of FF3 is coupled through bus drivers

G17. This causes OE-N to go high. The

U51 which generates SRLD-N. In response

next trailing edge of Q2-P causes OA-N to

to SRLD-N the Bus Controller causes SELD-N

go high and OB-N to go low. The next

to go low which is inverted by I14 and I15.

trailing edge of Q2-P causes OB-N to go

The output of I15 disables G18 and the out-

high and OC-N to go low. The next

put of I14 activates G19 which sets FF4

trailing edge of Q2-P causes OC-N to go

and enables gates G20 and G26. The 0 out-

high and OD-N to go low. The next

put of FF4 disables G21 preventing the

trailing edge of Q2-P cause; OD-N to go

precedance pulse, PCDA-P, (when re-

high which activates G17 again. OA-N

ceived) from being coupled through G21.

through OE-N are inverted by inverters I2

When PCDA-P is received, G26 is activated

and I4 through I8 which sequentially

which sets FF7 and FF8 and activates G20.

causes G3, G5, G7, G9, and Gil to be

The output of G20 resets FF3 which disables

enabled. The process repeats itself until

5-94