I/O CONTROLLER INFIBUS ACCESS LOGIC CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

SEL 2 goes high, RSJ enable 2 line driver

5 - 6 3 5 . When CCL BUS REQ (waveform G,

(40) is activated which causes RSJ EN 2 to

figure 96) goes high, the next positive

go high and RSJ EN 2 to go low for as long

going edge out of IS triggers this level into

as RSJ SEL 2 and RSJ BUS REQ are both high.

When RSJ SEL 3 goes high, RSJ enable 3

OBB-P goes high, G6 is activated which

line driver 40 is activated which causes

a c t i v a t e s Gl. The output of Gl activates

RSJ EN 3 to go high and RSJ EN 3 to go low

G2 causing shift register U54 to stop

for as long as RSJ EN 3 and RSJ BUS REQ

shifting data serially. OBB-P is activating

are both high.

G3 which disables the parallel load input

of shift register US4 as explained previously

5-638. I/O CONTROLLER INFIBUS ACCESS

The output of G6 is inverted by inverter

LOGIC CIRCUIT.

Ii which causes CCL BUS ACK to go high.

The output of G6 is also inverted by inver-

5 - 6 3 9 . General. The I/O Controller

ter I2 which activates the CCL enable line

INFIBUS access logic circuit detects when

driver U79 causing CCL EN to go high and

the RSJ or CCL function is requesting a

CC EN to go low. The I/O Controller inter-

direct memory access (DMA) request and,

face circuits remain in this state until CCL

in response, generates a direct data transfer

BUS REQ returns to low. The next positive

(DDT) INFIBUS access request. Also,

going edge out of I5 now triggers this level

during a DMA request, the INFIBUS access

into register U66 which disables G6. The

output of G6 now disables Gl which dis-

logic circuit detects whether the RSJ or

ables G2. The output of G2 now allows

CCL function is requesting a read (reading

shift register U54 to resume its normal

data from INFIBUS) or write (writing data

onto INFIBUS) operation. The I/O Control-

sequence of operations.

ler infibus access logic circuit also detects

5 - 6 3 6 . Operation of the I/O Controller

when the RSJ, CCL, or RMR function is gen-

interface circuit when RMR BUS REQ goes

erating an interrupt request and, in response,

high is similar to when CCL BUS REQ went

generates a level 2 interrupt INFIBUS access

high, except gate G7 is activated and shift

request. The INFIBUS access logic circuits

also couple the error signal (QUIT-N) to the

is high. The output of G7 is also inverted

RSJ and CCL functions.

by inverters I8 and I3, causing RMR BUS

5 - 6 4 0 . Detail Analysis (see figure 97).

ACK and RMR to go high for as long as RMR

The master reset pulse, MRES-N, is in-

BUS REQ is high.

verted by inverters I9 and I10. The output

5-637. Operation of the I/O Controller

of I10, GEN RESET-N (waveform B, figure

interface circuit when RSJ BUS REQ goes

98) is routed to the I/O Controller address

high is similar to when CCL BUS REQ went

recognition, done, and reset circuit and

high, except gate G5 is activated and shift

resets register U15 which disables gates

G3, G5, G7, G9, and G11. GEN RESET-N

high. The output of G5 is inverted by in-

is also inverted by inverter I5 which acti-

verter I6 which causes RSJ BUS ACK to go

vates gate G14 and enables the parallel

high. The output of G5 is also inverted by

load (L) input of shift register U4. The

inverter I1 which enables RSJ enable 1, RSJ

output of G14 disables the serial shift

enable 2, and RSJ enable 3 line drivers

input (S) of shift register U4. Disabling

U79 and U40. RSJ BUS ACK is high and the

G3, G5, G7, G9 and G11 disables gates

RSJ enable 1, RSJ enable 2, and RSJ enable

G4, G6, G8, G10, and G12. The low out-

3 are enabled for as long as RSJ BUS REQ

put of gate G15, DMAREQ-P, is inverted

is high as explained previously when CCL

by inverter Ill. The output of Ill is inverted

BUS REO was high. When RSJ SEL 1 goes

by I13 which resets flip-flop FF3. The low

high, RSJ enable 1 line driver U79 is acti-

output of Gl6, INTREQ-P, is inverted by

vated which causes RSJ EN1 to go high and

inverter I16. The output of I16 is inverted

by inverter I18 which resets flip-flop FF6.

The low output of Gl3 activates gate G2

5-93