I/O CONTROLLER DATA CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 9967-464-0010

5-620. When the I/O Controller is being

activates G21 causing DONE-N to be gen-

written into, under control of the stored

erated and register U58 and FFl to be reset

software program, to select the CCL func-

a s explained previously.

tion, G17 is activated (ABOO-N through

AB03-N equals decimal 2). When register

5 - 6 2 3 . If RITE-P is high and decimal 12

U58 is triggered by SSl, the Q3 output of

is on the INFIBUS address lines ABOO-N

through AB03-N, G19 is activated and the

G 1 1 . The output of G11 activates G12

output of register U58, RMR PDT SEL-P,

which generates CCL RESET-N and CCL

g o e s h i g h . RITE-P enables gate G26 and

RESET, as explained previously. The Q3

HMR PDT SEL-P activates G26 which trig-

output of register U58 is also inverted by

gers single shot SS3. 175 nsec after SS3

inverter I12 which generates CCL STAT

is triggered, FF2 sets which activates

SEL-N and the output of I6 is inverted by

gate G27 and enables gate G24. The out-

inverter I7 which generates CCL STAT SEL.

put of G27, RMR DT REQ, notifies the

Under these conditions the CCL function is

RMR function that an RMR data request is

s e l e c t e d a n d r e s e t . CCL STAT SEL-N acti-

b e i n g m a d e . In response to RMR DT REQ

going low, the RMR function causes RMR

vates G20 which causes DONE-N to be

DT RES to go low. R M R D T R E S i s i n v e r t e d

generated and register U58 and FFl to be

by inverter I20 which activates G24. The

reset, as explained previously.

output of G24 activates G21 which causes

DONE-N to be generated as explained pre-

5 - 6 2 1 . When the I/O Controller is being

viously.

written into, under control of the stored

software program, to select the RMR func-

5 - 6 2 4 . If READ-P is high and decimal 12

t i o n , G16 is activated (ABOO-N through

is on the INFIBUS address lines ABOO-N

AB03-N equals decimal 4). When register

through ABO3-N, RMR PDT SEL-P is gener-

U58 is triggered by SSl, the Q4 output of

ated as explained previously. READ-P en-

a b l e s gate G26 and RMR PDT SEL-P activates

The output of G14 activates G15 which

generates RMR RESET-N and RMR RESET, as

gate G26. The output of G26 enables gate

explained previously. The Q3 output of

G25 a n d a c t i v a t e s G 2 7 . The output of G27,

RMR DT REQ, causes the RMR function to

g e n e r a t e R M R D T R E S . R M R D T R E S I S in-

I14 which generates RMR STAT SEL-N and

verted by I20 which activates G25. The

the output of I14 is inverted by inverter I15

output of G25 causes DONE-N to be qener-

which generates RMR STAT SEL. Under

ated 600 nsec after G25 is activaated, as

these conditions the RMR function is selected

explained previously.

a n d r e s e t . RMR STAT SEL-N also activates

G20 which causes DONE-N to be generated

I/O CONTROLLER DATA CIRCUIT.

5-625.

and register U58 and FF1 to be reset, as

explained previously.

5-90