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Page Title:
I/O CONTROLLER ADDRESS RECOGNITION, DONE, AND RESET CIRCUIT |
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 T.O. 3135-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
detected on the INFIBUS, the I/O Controller
AB02-N and AB03-N are low and ABOO-N
and ABOl-N are high (decimal 12), the 12
INFIBUS
access circuit generates GEN
output of BCD-to-decimal decoder U22
RESET-N. GEN RESET-N activates gates
activates G19.
G9, G12, and Gl5. The output of G9 is
inverted by inverter I5 which generates
5-617. When STRB-P from the INFIBUS
RSJ RESET-N and RSJ RESET. Activating
access logic circuits goes high, register
G12 generates CCL RESET-N and CCL
U58, flip-flop FFl and gate G22 are en-
RESET and activating G15 generates RMR
abled and single shot SSl is triggered.
RESET-N and RMR RESET.
175 nsec after SS1 is triggered its output
returns to high which triggers register U58
5-615. When address F88X l6 (AB07-N
clocking the output of G13, G18, G17 and
and AB11-N through AB15-N low) is on the
G19, or G16 into the register U58.
INFIBUS address lines gate G4 is activated.
Address bits AB12-N through AB15-N are
5-618. When the I/O Controller is being
coupled through and inverted by the address
written into, under control of the stored
receivers U13, U26, U39, and US2 to acti-
software program, to select the RMR, CCL,
vate gate G4. Address bits AB08-N through
or RSJ function; RITE-P is high which en-
AB11 -N are inverted and coupled through
ables gates Gl through G3 and G8, G11,
the address receivers and address bits
and G14.
AB08-N through AB10-N are also inverted
by inverters I2, I3, and I4 to activate gate
5-619. When the I/O Controller is being
G7. Address bits AB04-N through ABO7-N
written into, under software program con-
are inverted and coupled through the address
trol. to select the RSJ function, G18 is
receivers and address bits AB04-N through
activated (ABOO-N through AB03-N equal
ABO6-N are also coupled through inverters
decimal 0). When register U58 is triggered
I9 through Ill to activate gate G10. The
by SSl, the Q2 output of register U58 goes
outputs of G4 and G7 activate gate G5 and
The output of
high which activates G8.
the output of G10 is inverted by inverter
G8 activates G9 which generates RSJ RESET-
I8.
The high outputs of G5 and I8 activate
N and RSJ RESET, as explained previously.
gate G6 which enables gates G13, G18,
The Q2 output of register U58 is also in-
G17, G16, and G19 and generates F88-N.
verted by inverter I6 which generates RSJ
F88-N causes the I/O Controller INFIBUS
STAT SEL-N and the output of I6 is inverted
access circuit to generate BUSEN-P which
by inverter I7 which generates RSJ STAT
enables gate G23.
SEL. Under these conditions the RSJ func-
tion is selected and reset. RSJ STAT SEL-N
5-616. Address bits ABOO-N through AB03-N
activates gate G20 which triggers single
are inverted and coupled through the ad-
dress receivers and routed to BDC-to-decimal
decoders U21 and U22. The AB03-N output
of the address receivers is inverted by in-
verter I16 before it is applied to BCD-to-
decimal decoder U22. If ABOO-N through
AB03-N are low (decimal 0), the 0 output
of the BCD-to-decimal decoder U21 acti-
v a t e s G 1 8 . If AB02-N is low and ABOO-N,
ABOl-N, and AB03-N are high (decimal 2),
the 2 output of BCD-to-decimal decoder
U 2 1 a c t i v a t e s G 1 7 . If A802-N is low and
ABOO-N, ABOl-N and AB03-N are high
(decimal 4), the 4 output. of BCD-to-decimal
decoder U21 activates G16. If ABOl-N
and AB02-N are low and ABOO-N and AB03-N
are high (decimal 6), the 6 output of BCD-
to-decimal decoder U21 activates G13. If
5-89
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