I/O CONTROLLER DATA CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

3, 5, 6, 7, 8 is set by CCL CMND CLK-P.

flip-flops FFl, FF3, FF5 through FF7 and

Also, if any one or more, but not ail data

FF9. RMR RESET-N activates gate G18

bits DB02-P through DBOG-P are low, the

which resets flip-flops FF10 through FF13

output of gate G6 is low which disables

and FF14.

gate G9. This low output of G6 is in-

verted by inverter I11 which enables gates

5-628. When the I/@ Controller is being

G7 and G8. If DB07-P is high at this time,

written into (RITE-N low) and when address

G7 is activated enabling FF8 to be set. If

recognition occurs, RSJ CMND CLK-P, CCL

DBO7-P is low at this time, it is inverted

CMND CLK-P, and RMR CMND CLK-P are

by inverter I13 which activates G8 enabling

generated simultaneously by the I/O Con-

troller address recognition, done and reset

FF8 to be cleared, if necessary, by CCL

circuit. The leading edges of RSJ CMND

CMND CLK-P. If data bits DB02-P through

CLK-P, CCL C MND CLK-P, and RMR CMND

DBOG-P are low, the output of G6 is high,

which enables G9. If DB07-P is high at

CLK-P trigger FFl through FF14, clocking

this time, G9 is activated. The output of

the associated input data into the flip-flops.

G9 enables G10 to be activated by CCL

On the trailing edges of RSJ CMND CLK-P,

CMND CLK-P. The output of G10 activates

CCL CMND CLK-P, and RMR CMND CLK-P

G11 which resets FF8. The output of G11

(when I/O Controller address removed from

also activates G12 which resets FFl, FF3,

INFIBUS address lines) the output of the

FF5 through FF7 and FF9. If DB15-N is

appropriate flip-flops change state gener-

low, DB15-P is high which enables FF9 to

ating the appropriate command word to the

be set by CCL CMND CLK-P. The outputs

RSJ, CCL, or RMR functions.

of FFl, FF3, and FF5 through FF8 are in-

5-629. If data bit DBOO-N is low and data

verted by inverters I1 through I12, respec-

bit DBOP-N is high, DBOO-P is high and

tively. The output of I1, DOTST, is routed

DBOl-P is low. DBOO-P enables gates G1

to the CCL function. The output of I4,

and G2 and enables FF2 to be set by RSJ

D040, commands the CCL function to exa-

CMND CLK-P. DBOl-P disables G1 and is

mine and update all transition leads. The

inverted by inverter I7. The output of I7

output of I6, D01 commands the CCL func-

activates G2 which enables FF4 to be

tion to examine and update all transition

cleared by RSJ CMND CLK-P, if necessary.

and 1 second usage/duration leads. The

The trailing edge of RSJ CMND CLK-P sets

output of I9, D010, commands the CCL

FF2 and ensures FF4 is cleared. The output

function to examine and update all transi-

of FF2 is inverted by inverter I3 causing

tion, 1 second and lu second usage/duration

DORSJ to go low. DORSJ notifies the RSJ

leads. The output of I10, DOCALL, com-

function to perform a traffic or call data

mands the CCL function to operate in the

collection operation. When DBOO-N and

call data collection mode. The output of

DBOl-N are low, DBOO-P and DBOl-P are

I12, CCL INT INH, prevents the CCL func-

high which activates gate G1. Under these

tion from requesting INFIBUS access,, The

conditions, the trailing edge of RSJ C MND

output of FF9 is inverted by inverter I15.

CLK-P sets FF2 and FF4. With FF2 and

The output of I15, TOG, specifies the

FF4 set, DORSJ and RSJ INT INH are gener-

exact location in Core Memory where the

ated by inverters I3 and I5, respectively.

last transition count is stored. When SCAN

With DORSJ and RSJ INT INH low, the RST

COMPLETE (high) is received, it is in-

function is enabled by DORSJ and INT

verted by inverter I14 which activates G12.

INH prevents the RSJ function from generating

The output of G12 resets FFl, FF3, FF5

a request for INFIBUS access.

through FF7 and FF9.

5-630. Data bits DB02-N through DB07-N

5-631. When DB08-P is high, FF10 is

are coupled through and inverted by data

enabled to be set by RMR CMND CLK-P.

bus receivers U64 and U78, generating

Data bits DB08-N throuqh DB13-N and

DB02-P through DB07-P. If any one or

DB15-N are coupled through and inverted

more of the data bits DBOO-P through DB06-

by the data bus receivers U91 and U65.

P are high the associated flip-flop, FFl,

DB09-P enables FF11, DB10-P enables FF12,

5-91