MAG TAPE CONTROLLER A1A3A14 ADDRESS RECEIVERS AND RECOGNITION CIRCUIT

T.O. 31S5-4-308-I

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

and U67 select the address register data

must be high which activates Gate G2. The

(AOOA-N, A0lA-N, AO6A-N and A07A-N) and

combined outputs of the address recogni-

data multiplexers U56, U68 and U79 select

tion gates U19, U28, and U39, DRl, and

G2 will be high which places a high at the

the address register data (A02A-N through

set input of flip-flop FFl.

AO5A-N and A08A-N through A15A-N).

MOOX-N through M15X-N are generated as

determined by the levels of AOOA-N through

5-555. Inverters I2, I3, and I5, and gates

A15A-N and routed to data bus driver/

G3 through G6 decode AOlA-P, A02A-P, and

receivers U60, U69, U70, and U80. ASTA-P

A03A-P to select the control, status, or

strobes data bus driver receivers U60, U70

data registers in the Mag Tape Controller

and U80. ASTB-P strobes data bus driver

data output and control register circuits.

receiver U69 which generates DBOO-N

To select the control register, AOlA-P and

through DB15-N.

A02A-P are high and A03A-P is low. Gate

G4 is enabled by AOlA-P and A02A-P and

5-551.

MAG TAPE CONTROLLER A1A3A14

the high output of I5. G4 is activated and

ADDRESS RECEIVERS AND RECOG-

generates ACNT-N when FFl is set. To

NITION CIRCUIT.

select the status register, AOlA-P, A02A-P

and A03A-P are all low and the high outputs

of I2, I3, and I7 enable G5. When FFl

5 - 5 5 2 . General. The Mag Tape Controller

sets, G5 is activated which generates

address receivers and recognition circuits

AWST-N. To select the data register,

recognizes the Mag Tape Controller address

AOlA-P and A02A-P are low and A03A-P is

when being slaved by a master function. It

high. G6 is enabled by the outputs of I2

selects the internal registers of the Mag

and I3, and A02A-P. When FFl is set, G6

Tape Controller and performs a read or write

will be activated which generates ADAT-P.

operation as determined by the master func-

Gate G7 will be disabled if the correct

tion slaving the Mag Tape Controller.

combination of AOlA-P, A02A-P and A03A-P

5-553. Detail Analysis (see figure 79).

are received to select one of the Mag Tape

Controller internal registers.

The device number connector J3 connections

determine the Mag Tape Controller address

(device number). DN04-N through DN11 -N,

5 - 5 5 6 . When data is to be loaded into the

Mag Tape Controller data register, the

device number bits, are routed to the Mag

master function generates the address

Tape Controller data input and selector cir-

(waveform A, figure 42), data, strobe and

cuit to be placed on the INFIBUS data lines

RITE-N (waveform B, figure 42) on the

when the Mag Tape Controller is requesting

INFIBUS. The address will be recognized

a level 3 INFIBUS access. The device num-

which enables FFl to be set as explained

ber inverters (19 shown) generate DA04-P

previously. G3 generates AABL-P (wave-

through DA11-P. ABOl-N through AB15-N

form C, figure 42) and enables the set input

from the INFIBUS address lines are inverted

of flip-flop FF2. RITE-N is inverted by

by address bus receivers U10, U20, U29,

and U40 (11 shown) which generate AOlA-P

inverter I11 which enables G7 and G10.

The output of I11 is also inverted by inver-

through A15A-P .

ter I12 which disables gate G11 and

ARED-P goes low. If the Formatter is

5-554. A04A-P through A11A-P are applied

ready to accept data, WBAR-N IS low

to the address recognition gates U19, U28,

which disables gate G7. The high output

and U39 (Gl shown) where they are com-

of G7 enables gate G8. The Mag Tape

pared with the jumper encoded device num-

Controller INFIBUS access circuit gener-

ber (DA04-P through DA11-P). If there is

ates STRA-P (waveform D, figure 42) which

a match at the inputs, the corresponding

IS coupled through driver DR2. The output

outputs of the address recognition gates

DR2 is coupled through driver DR3 then

U19, U28, and U39 will be high. Also,

delayed 50 nsec by delay DL4. The output

for address recognition, A12A-P must be

of DL4 activates gate G8 which triggers

high which is coupled through driver DRl.

and sets FF1. If the Formmatter is not ready

In addition A13A-P, A13A-P and A15A-P

5-80