BLOCK-TRANSFER ADAPTER A1A3A13 ADDRESS, DATA, AND BLOCK LENGTH CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

and CLBR-N), or control register (BTA con-

5 - 5 4 5 . When the data on the INFIBUS data

trol circuit ABAR-N and AMDR-N).

lines is the block length (number of words

to be transferred to or from the Core Mem-

5 - 5 4 7 . When the status register is to be

or-y), ALDB-N goes low parallel loading

read out of the BTA onto the INFIBUS data

block length registers/counters U54, U62,

lines, A02A-P and AOlA-P will be low

U63, and U76 with the number determined

which couples CBLR-N to M07X-N, ABTR-N

by DOOA-P through Dl5A-P. Block register/

to MOGX-N and 5 volts to MOlX-N. Also,

counters U54, U62, U63, and U77 operation

MOOX-N, MOlX-N, MOGX-N, and M07X-N

is similar to the address register/counters

are routed to bus driver receiver U69. After

U53, U64, U65, and U76, except they

address recognition by the BTA control cir-

count down and the MIN output enables the

cuit, ASTB-P is generated and strobes data

next block length register counter. The

bus driver receiver U69 which generates

outputs of block length register/counters

DBOO-N, DBOl-N, DBO6-N, and DB07-N.

U54, U62, U63, and U77 are inverted by

At the same time data multiplexers U56,

inverters I18 through I34 generating LOOA-N

through Ll5A-N which are applied to data

U68 and U79 select the address register

data (A02B-N through AO5B-N and A08B-N

multiplexers U56, U66, U67, U68 and U79

through A15B-N) and M02X-N through

for selection. U62 is always enabled and

M05X-N and M08X-N through Ml5X-N are

CDEC-N clocks all four counters simul-

routed to data bus driver receivers U6O, U70

taneously. On the first 16 CDEC-N inputs

and U80, but will not be strobed onto the INPI-

block length register/counter U62 will

BUS data lines because ASTA-P is not gener-

decrement from 15 to 0 (binary) and on the

0 count, the MIN (minimum) output of U62

ated.

will go high. I26 inverts this output which

5 - 5 4 8 . To read out the control register con-

enables U63 to decrement once on the next

tents of the BTA, operation is similar to

CDEC-N input. The cycle will be repeated

until block length register/counters U62 and

when the status register is read, except

U63 are decremented to 0 and both of their

A0lA-P and A02A-P are high which couples

ABAR-N to M07X-N, 5 volts to M06X-N,

MIN outputs will be high. G4 is now acti-

vated which enables block length register/

AMDR-N to MOlX-N, and 5 volts to MOOX-N

counter U54 to decrement on the next

bit posit ion. They are routed to data bus

CDEC-N input. The cycle will be repeated

driver receiver U69 and strobed to the INFI-

until block length register/counters U54,

BUS data lines by ASTB-P. At the same

U62, and U63 are at 0 and the MIN outputs

time, data multiplexers U56, U68 and U79

are high activating G3. G3 enables block

select the block length register data

length register/counter U77 to decrement

(L02A-N through LO5A-N and L08A-N through

once on the next CDEC-N input. Again, the

L15A-N), but this data is not strobed out

entire cycle will be repeated until all four

because ASTA-P is not generated.

block length register/counters are at 0 and

the MIN outputs are high activating G5.

5 - 5 4 9 . To read out the block length regis-

The output of LAZE-N, is routed to the BTA

ter data (LOOA-N through L15A-N), AOlA-P

control circuit indicating the block length

is low and A02A-P is high and LOOA-N

through L15A-N are coupled through data

verts LAZE-N generating LAZD-P which is

multiplexers U58, U66, U67, U68, and

routed to the BTA control circuit. These

U79 which generate MOOX-N through M15X-P.

outputs notify the BTA control circuit that

ASTB-P strobes bus driver/receiver U69 and

the entire block of data transfers has been

ASTA-P strobes bus driver/receivers U60,

completed.

U70, and U80 which generate DBOO-N through

D B l 5 - N . LOOA-P through L15A-P determine

5-546. Data multiplexers U56, U66, U67,

the levels of DBOO-N through DB15-N.

U68, and U79 select data from the block

length register (LOOA-N through Ll5A-N),

5 - 5 5 0 . To read out the address register data

address register (A00B-N through Al5B-N),

(AOOB-N through A15B-N), A02A-P is low

status register BTA control circuit ABTR-N

and A0lA-P is high. Data multiplexers U66

5-79