BLOCK-TRANSFER ADAPTER A1A3A13 ADDRESS, DATA, AND BLOCK LENGTH CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

previously. The 1 output of FF12 acti-

5-543. Address data, AOOB-N through

vates G29 which activates G30 and

Al5B-P, stored in the address register/

BTB4-B is generated, as explained

counters U53, U64, U65, and U76 are in-

previously.

verted by inverters I2 through I17 and is ap-

plied to address bus driver receivers U10,

5-540. BLOCK-TRANSFER ADAPTER A1A3A13

Ul9, U20, and U30. BOLA-P from the BTA

ADDRESS, DATA, AND BLOCK

control circuits strobes address bus driver

LENGTH CIRCUIT.

receivers UlO, U19, U20, and U30 when

information is to be transferred to the

5-541. General. The Block Transfer

INFIBUS, generating ABOl-N through ABl5-N

Adapter (BTA) address, data, and block

as determined by the data (or count) in

length circuit consists of the address bus

address register/counters U53, U64, U65,

driver receivers, address register, block

and U76.

length register, data bus driver receivers,

and data multiplexer. Address data is re-

5-544. When the starting address is on the

ceived or transmitted by the address bus

INFIBUS data lines DBOO-N through DBl5-N

driver receivers and the address register

are coupled through the data bus driver re-

holds the Core Memory address to or from

ceivers generating DOOA-P through Dl5A-P.

which data is to be transferred or device

AMAR-N goes low, parallel loading address

address (device number). The number of

data transfers to be performed is stored in

with the number determined by DOOA-P

the block length register and the data to

through Dl5A-P. For each transfer of data

be transferred to or from the INFIBUS data

to or from the Core Memory, CCKA-N is

lines is first selected by the data multi-

generated by the BTA control circuits and

plexer then strobed to the INFIBUS via the

is applied to the clock inputs of the four

data bus driver receivers. This circuit also

address registers/counters. Address regis-

generates increasing addresses. Each

ter/counter U65 is clocked and counts 0 to

transfer of data to or from Core Memory in-

15, generating its carry output on the

creases the address and decreases the block

fifteenth count. The carry output of address

length by one. When the maximum address

or zero block length is reached, the trans-

1 on the sixteenth CCKA-N input and ad-

fers stop.

dress register/counter U65 resets to zero.

This cycle repeats itself until address

5-542. Detail Analysis (see figure 78).

The address bus driver receivers U10, U19,

U20, and U30 transmit and receive the 16-

fully loaded (count equals 256, the carry

bit address. (AB00-N through ABl5-N).

outputs of address register/counters U64

Address bits ABOl-N through ABl5-N are in-

and U65 enable address register counter

U53 to count 1. This cycle repeats itself

verted by address bus driver receivers Ul0,

until address register/counters U53, U64,

U19, U20, and U30 (inverter I1) generating

and U65 are fully loaded (count equals 4096).

AOlA-P through Al5A-P. The O-bit position

is not an input to the BTA. AOlA-P through

The carry outputs of address register coun-

ters U53, U64, and U65 will be generated

Al5A-P are routed to the BTA control cir-

enabling U76 to count 1. The cycle repeats

cuits for address (device number) recogni-

itself until all four address register/counters

tion. AOlA-P and A02A-P are also applied

are fully loaded (count equals 65, 536)

to the select inputs of the data multiplexers

With address register/counter U76 fully

U58, U66 and U67, U68, and U79. In a

read cycle of the BTA contents, the address

loaded (all outputs high), 62 is activated

generating AFXA-N which is routed to the

recognition logic receives the address for

BTA control circuits. AFXA-N prevents the

recognition and at the same time the data

BTA control circuits from generating any

multiplexers will select the data to be

more CCKA-N clock pulses. There is one

placed on INFIBUS data lines as determined

CCKA-N input for each byte transfer.

by the levels of AOlA-P and A02A-P.

5-78