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T . O . 3lS5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
high and LAZE-N low), FF12 will set. If
Controller also receives DONE-N and
the block length register is not at zero,
strobes the data from the INFIBUS data lines
LAZD-P is low and LAZE-N is high and FF14
into its output data register, presenting the
is set.
data to the Formatter. As BDNA-P is gener-
ated, FF15 is set because BOLA-P is being
5 - 5 3 6 . If there is to be another transfer
generated at this time, which enables the
(the block transfer not completed), LAZE-N
set input. G38 is activated by the 0 output
input is high and only FF14 will be set.
of FF15 which presets FF19. CEXR-N (wave-
With FF11 enabling G36, the 1 output of
form S, figure 77), is generated by FFl9 and
FF14 activates G36 which enables G35.
On the trailing edge of
d i s a b l e s Gl.
When the Formatter notifies the Mag Tape
BDNA-P, G26 and G27 are disabled. I14
Controller to perform another transfer,
now activates G23, which clears FF5. The
BTBl-N is again received and inverted by
0 output of FF5 enables G18 and the 1 out-
I21. This activates G35 which generates
put of FF5 disables G27, G22 and G26 and
CCSN-P and the entire sequence is repeated
resets FF6. The output of G27 now disables
for the next data word to be written.
G24, G28 and G44. G28 removes STRB-N and
G44 removes BYTE-N. With STRB-N removed
5-537.  When all the transfers are com-
STRA-P is also removed which disables G22
pleted, LAZD-P and LAZE-N are generated
and I13 once again enables G20.
and as FF12 and FF14 are clocked, only
FF12 is set. The 0 output (low) of FF12,
5-535. When CEXR-N is generated by FF19,
CBLR-N, is routed to the BTA address, data
FFl5 is set. I22 inverts CLKA-N (waveform
and block length register circuit to be
Q, figure 77) and FF16 will be set on the
placed in the seventh bit position of the
next high-to-low transition of the output of
data word when the status register is read
I29. The 1 output of FF16 enables its own
to indicate the completion of transfers. The
clear input and the set input of FF17. Also,
1 output of FF12 enables G29 and G31. On
gares G40 and G41 are activated because
the next request G29 (BTBl-N) is activated
LAZE-N is only generated when the block
which activates G30. The output of G30
length register is at zero (all transfers com-
activates G33 which activates G31. G31
pleted) and AFXA-N is only generated when
generates BTB4-N (waveform Z, figure 77)
the address register is fully incremented
which is a request to the Mag Tape Control-
(the required addresses completed). The
output of G40, CDEC-N (waveform U,
ler to generate a level 3 interrupt to indicate
figure 77), decrements the block length
to the CPU that the entire block of data
register and the output of G41 activates
words has been transferred.
G42 which generates CCKA-N (waveform V,
figure 77). CCKA-N clocks (increments)
5-538. If after or during the write opera-
tion, a timing error occurs in the Mag Tape
the address register. At the same time,
Controller, BTB3-N will be generated which
the 0 output of FF16 activates G39 which
indicates an error condition. I20 inverts
clears FF15. On the next high-to-low
BTB3-N which triggers and sets FF10. The
transition output of I22, FF16 is cleared
and FF17 is set. G40, G41, and G42 are
output of FF10 disables G35 and activates
G33. The output of G33 activates G31
disabled, which removes CDEC-N and
CCKA-N. On the next nigh-to-low transi-
which generates BTB4-N, as explained
previously.
tion output of I22, FF17 is cleared and
FF18 is set. FF18 generates CX3R-N (wave-
form Y, figure 77) which activates gate G32
5 - 5 3 9 . During read operation of the
and on the next high-to-low transition out-
Formatter, operation is similar to a
put of I22, FF18 clears which removes
write operation. When loading the control
CX3R-N.  The low-to-high transition of
register, the l-bit position (DO1A-P)
CEXR-N clears FFl9 and also disables G32.
will be low and FF8 is not set. The 0
FF12 and FF14 are clocked by the high-to-
output (high) of FF8 enables G30 and
low output transition of G32 and if the
when the specified number of transfers are
block length register is at zero (LAZD-P
completed, FF12 is set, as explained
5-77

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