BLOCK TRANSFER ADAPTER A1A3A13 CONTROL CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

FF14 set) which generates CCSN-P (wave-

5 - 5 3 2 . The Bus Controller will generate

form B, figure 77). If the INFIBUS is not

QUIT-N if the transfer is not completed

busy, SELD-N will be high which enables

within 2 usec. Inverter I16 inverts QUIT-N

gate G18. As CCSN-P is generated G18

which activates gate G25. G25 sets FF7

will be activated. The output of G18 sets

which generates BABR-N which triggers and

FF3. The 1 output of FF3, enables gates

sets FF13. The output of FF13 activates

G16 and G19 and activates gate G15. The

gate G33 which activates gate G31. The

output of G15 is coupled through driver DR4.

output of G31, BT4B-N, causes the Mag

The output of DR4, SRLD-N (waveform C,

Tape Controller to generate a level 3 inter-

figure 77) is the highest priority infibus

rupt request. This halts the current opera-

access request and the Bus Controller de-

tion and the CPU tests status to initiate

tects this request and responds with SELD-N

the operation once again.

(waveform D, figure 77) and PCDA-P (wave-

form E, figure 77). SELD-N disables G18

5-533. In a normal cycle (within 2 usec),

and is also inverted by inverter I12 which

BOLA-P enables G28 and BOLA-P is also

enables G19 and activates G16. With G16

inverted by inverter I15. After the 50 nsec

activated, G17 is disabled and PCDB-P is

delay of delay DL4, G28 is activated by

not generated. PCDA-P activates G19

the output of I15 which generates STRB-N

which sets FF4 and disables gate G21.

(waveform K, figure 77). With the strobe

The 1 output of FF4 activates gate G20 and

(STRB-N) generated, the Core Memory will

generate the data from the address gener-

enables G21. The 0 output of FF4 disables

G18 and G15 and activates driver DR3

ated by the BTA. It will take approximately

which generates SACK-N (waveform P,

325 nsec for the Core Memory to place the

figure 77). Disabling G15 causes SRLD-N

data on the INFIBUS data lines. As

to return to high. The Bus Controller then

STRB-N is generated, inverter I18 inverts

removes PCDA-P and G19 is disabled which

STRB-N and generates STRA-P (waveform

activates G21. G21 resets FF3 and G15 and

L, figure 77) which activates G22,

G16 will be disabled by the 1 output of FF3

clearing FF4. Inverter I13 also inverts

(low). With G16 disabled, G17 is once

STRA-P, disabling G20. At the same time,

again enabled to generate PCDB-P. SELD-N

the 0 output (low) of FF5 disables G18 and

is then removed by the Bus Controller

the 1 output (high) enables G26 and acti-

which enables G18 and it is also inverted

vates G27. G27 activates G24 and the

by I12 which disables G16 and G19. At

output of G27 is also routed to the

the same time, the 1 output (high) of FF4

INFIBUS as BTB2-N (waveform J, figure 77).

BTB2-N notifies the Mag Tape Controller

activates gate G20. The output of G20 sets

to accept the data present on the INFIBUS

FF5 and activates gate G24. BOLA-P

(waveform G, figure 77) is generated by

data lines and present it to the Formatter.

G24 -which is routed to the BTA address,

BTB2-N (BOND-N) also activates G37

which resets FF14. The 1 output (low)

data and block length register circuit to

strobe the first address of the address regis-

of FF14 disables G36 which disables

ter to the INFIBUS (waveform l-l, figure 77).

G35, removing CCSN-P.

BOLA-P does not activate G4 because

AMOS-P is being generated for a write

5 - 5 3 4 . The Core Memory, having receiving

operation (presenting data to the Formatter),

an address with the RITE-N line high (read),

will generate the data from the address

disabling G4. BOLA-P also activates G43

specified. After the dats is stabilized on

which generates BYTE-N (waveform I,

the INFIBUS data lines, the Core Memory

figure 77). G25 is also enabled by BOLA-P

Controller generates DONE-N (waveform

and will is activated if the transfer is not

N, figure 77). inverter I19 inverts DONE-N

completed within 2 usec. In this cycle,

generating BDNA-P (waveform 0, figure 77)

data is to be read out of the Core Memory

which activates G27 and G26. Inverter I14

and RITE-N is high. The address is gener-

inverts BDNA-P, disabling G20 and G23.

ated and the Core Memory will present the

The output of G26 sets FF6 and the 1 output

data (from address selected) on the INFIBUS

(high) of FF6 enables G23. The Mag Tape

data lines.

5-76