BLOCK TRANSFER ADAPTER A1A3A13 CONTROL CIRCUIT-CONT.

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

activated and its output activates G10 which

I4 activates G2 which generates ADUN-N

generates ACNT-P (waveform G, figure 76).

(waveform I, figure 75). ADUN-N is coupled

Inverter Ill inverts ACNT-N which gener-

through driver DRS which generates DONE-N

ates ACWT-N (waveform H, figure 76). At

(waveform J, figure 75). The output of I5 is

this time, the BTA address, data, and

delayed by delay DL3 for 50 nsec which

block length register circuit is presenting

then disables G2, removing DONE-N. TO

the control word bits DOOA-P, DOlA-P and

read the contents of the address register,

D07A-P to the control register flip-flops

the Processor master function generates the

FF8, FF9, and FF11, respectively. The

address and RITE-N remains high. G5 and

leading edge of ACNT-P triggers FF11,

G7 are both enabled by the output of I7 and

loading it with D07A-P and on the trailing

G11. When FFl is set, AMAS-P activates

edge of ACNT-P FF9 is triggered, loading

G5 and G7 generating ASTB-P and ASTA-P,

it with DOOA-P. The 0 output (low) of FF9

respectively, to the BTA address, data and

activates gate G32. On the trailing edge

block length register circuit to strobe the

of ACWT-N, FF8 is triggered loading it

address register contents to the INFIBUS

with DOlA-P. On the trailing edge of

data lines and DONE-N is generated as

AMAS-P (waveform F, figure 76), FF9 is

explained previously.

cleared and G32 is disabled. The high-to

low transition output of G32 triggers flip-

5-529. To load the block length register

flops FF12 and FF 14. If the block length

within the BTA address, data and block

length register circuit, the Processor

address, data, and block length register

master function places the address, data

and RITE-N on the INFIBUS. G3 and G8 are

circuit is high which enables the set input

of FF14. FF14 is set by the high-to-low

enabled and address recognition takes place,

G3 is activated which activates G8, gener-

transition output of G32 and the 1 output

ating ALDB-N (waveform G, figure 74) to the

(high) of FF14 enables gate G36. The 1

BTA address, data and block length register

output (high) of FF11 enables gate G31 and

circuit. This action loads the block length

activates G36 which enables gate G35.

The 0 output of FF11, ABAR-N, is routed to

lines. FF2 is triggered and set by the output

the BTA address, data and block length

of I2 and the 1 output of FF2 enables G2,

I4 activates G2 which generates ADUN-N

(waveform H, figure 74). ADUN-N is

The 1 output, AMDS-P, of FF8 enables gate

coupled through DR.5 which generates

G30 and disables gate G4. The 0 output,

DONE-N (waveform I, figure 74) and after

AMDR-N, of FF8 disables G30 and is also

the 50 nsec delay of DL3, G2 is disabled

routed to the BTA address, data and block

and DONE-N is removed. To read the con-

length register circuit. For a read o p e r a t i o n

tents of the block length register, the Pro-

DOlA-P is low and FF8 is not set. AMDS-P

cessor master function generates the ad-

(low) disables G30 and enables G4. The Mag

dress and RITE-N remains high. G5 and G7

Tape Controller cycles, loading its control

are enabled by the output of I7 and G11.

When FFl is set, G5 and G7 are activated

INFIBUS. To read the control register

which generates ASTB-P and ASTA-P to the

contents, the cycle is repeated as explained

BTA address, data and block length regis-

previously for reading the status register,

ter circuit which strobes the block length

but the BTA address, data and block length

DONE-N is generated, as explained previ-

the INFIBUS.

ously.

5-531. The Mag Tape Controller will

5-530. TO load the control register, the

generate a request for data when instructed

Processor master function generates the

by the Formatter and BTBl-N (waveform A,

address, control word, and RITE-N. Ad-

figure 77) will be received (BTAl-N from

dress recognition takes place and G10 is

the Mag Tape Controller). Inverter I21 in-

enabled as explained previously. G3 is

verts BTBl-N activating gate G35 (FF11 and

5-75