BLOCK TRANSFER ADAPTER A1A3A13 CONTROL CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 1l-5805-663-14-13

NAVELEX 0967-464-0010

on the INFIBUS, driver DR3 is activated

(waveform C, figure 72) which generates

and its output activates gate G14. G14

STRA-P (waveform D, figure 72). STRA-P is

generates ACIA-N which resets flip-flops

coupled through drivers DR1 and DR2 and

FF3 through FF6, FF8, FF10, FF11, FF12

inverter I8 inverts the output of DR2 which

via gate G34, FF14 via gate G37, FF15 via

triggers and sets FFl. The 1 output (high)

gate G39, and FF16 through FF19.

of FFl activates gate G1 which activates

G3. Inverter I1 inverts the output of G1

5-524. For address recognition, the ad-

and the output of I1 is delayed by delay

dress comparators U9, U17, and U18 com-

DL2 for 50 nsec. Then, inverter I2 inverts

pare the jumper encoded address of Jl with

the output of DL2 and the output of I2 is

the address bits AO3A-P through Al5A-P

inverted by inverter I3 which disables G3.

from the BTA address, data and block length

The output of G3 activates G13 which acti-

vates G14, generating ACLA-N (waveform

are always high for a Processor function

G, figure 72) which resets the BTA control

address and the output of gate G12 is high.

circuits as explained previously.

If there is address recognition, the outputs

of the address comparators are high which

5-527. To read the status register, the

places a high at the set input of flip-flop

Processor master function generates the ad-

FFl. Address bits A0lA-P and A02A-P from

dress and does not generate RITE-N (wave-

the BTA address, data and block length cir-

form B, figure 73) on the INFIBUS. Address

cuit are decoded to select the BTA internal

recognition occurs and G5 is enabled and

registers. To select the status register,

G7 is disabled as explained previously.

A0lA-P and A02A-P are low and the outputs

The Processor master function generates

of inverters I9 and I10 enable gate G13.

STRB-N and STRA-P (waveform D, figure 73)

Also the outputs of I9 and I10 activate gate

enables G5. FFl is set and the 1 output,

G11 which disables gate G7 and places a

AMAS-F, of FFl activates G5 which gener-

low at the set input of flip-flop FF2. To

ates ASTB-F (waveform E, figure 73).

select the control register, AOIA-P and

ASTB-P strobes the status data onto the

A02A-P are high which enables gate G10 and

INFIBUS.

G11 is again activated. To select the ad-

dress register, A0lA-P is high and A02A-P

5 - 5 2 8 . To load the address register within

is low. AOlA-P and the output of I9 enables

the BTA address, data and block length

gate G9 and G11 is not activated which

enables G7 and places a high on the set in-

tion generates the address, data and RITE-N

put of FF2. To select the block length regis-

on the INFIBUS. A d d r e s s r e c o g n i t i o n o c c u r s

ter, A0lA-P is low and A02A-P is high.

and G9 is enabled and G11 is not activated

A02A-P and the output of I10 enable gate

which enables the set input of FF2. The

G8 and G11 is not activated.

Processor master function generates STRB-N

on the INFIBUS and STRA-P sets FFl. F11

5 - 5 2 5 . To write into any of the internal

generates AMAR-N (waveform F, figure 75

registers, RITE-N (waveform B, figure 72

which is routed to the BTA address, data and

is generated on the INFIBUS and inverter

block length register circuit to enable the

I6 inverts RITE-N which enables gate G3.

address register to be loaded. G9 is acti-

To read any of the internal registers, RITE-N

vated by the output of G3 and G9 generates

is high and the output of I6 is inverted by

ALDA-N (waveform G, figure 75) which acti-

inverter I7 which enables gates G5 and G7.

vates gate G42. G42 generates CCKA-N

(waveform F-I, figure 75) which is routed to

5 - 5 2 6 . When the BTA status register IS

the BTA address, data and block length

written into, the address is placed on the

INFIBUS and RITE-N is generated by the

with the starting address that is on the

Processor master function. Address recog-

INFIBUS data lines. FF.2 is triggered and

set by the output of I2 and the 1 output

nition takes place and G10 and G13 are en-

(high) of FF2 enables gate G2. I3 disables

a b l e d . The Processor master function gener-

G3 and after the 50 nssec delay of delay DLl,

ates STRB-N and inverter I18 inverts STRB-N

5-74