BLOCK TRANSFER ADAPTER A1A3A13 CONTROL CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

high which enables G11 and RDTS-P is low

The output of G17, TRSE-P, is inverted by

which disables G9. When G6 is activated,

I2 which generates TRSA-N. TRSE-P and

as explained previously, G11 is activated

TRSA-N are routed to the data selector/

which enables the set input of FF5. On the

control circuit to enable the Serial I/O

next high-to-low transition of CLCK-P, FF5

data register to be serially loaded with

is set which generates RFER-N. RFER-N

data from the external device.

activates G12 which generates EROR-N.

EROR-N is routed to the INFIBUS access

5-516. With the set and clear inputs of

circuit, causing it to generate a format

FF2 both low, FF2 remains set with further

error interrupt request.

high to low transitions of CLCK-P. Every

seventh count of CLCK-P by the 4-bit binary

5 - 5 2 0 . If the data word is not read out of

counter causes the 6 and 7 decoder U21 and

the Serial I/O data register, the address

U51 to generate TRO7-P. TR07-P is routed

recognition circuit does not generate

to the data selector/control circuit and one

RCBA-N and FF3 remains set which enables

data bit from the external device is loaded

G10. When the next word is being received

into the data register.

from the external device, G2 is activated,

as explained previously, which activates

5 - 5 1 7 . When the entire word is loaded,

G10. The previous data word is destroyed

the start bit of the word causes the data

and G10 triggers and sets FF4 which gener-

selector/control circuit to generate DSTS-P

ates RQRR-N. RORR-N is routed to the

which enables G6. Also at the same time,

data selector/control circuit. RORR-N also

the stop bits of the word cause the data

activates G12 which generates EROR-N.

selector/control circuit to generate RDTR-N

EROR-N is routed to the INFIBUS access

and RDTS-P. RDTR-N disables Gl, G5,

circuit causing it to generate an overrun

and RDTS-P enables G9.

interrupt request.

5-518. On the next sixth count by the

BLOCK TRANSFER ADAPTER A1A3A13

5-521.

binary counter U42, the 6 output of the 6

CONTROL CIRCUIT.

and 7 decoder U21 and U51 activates G6

which enables the clear input of FF2 and

5 - 5 2 2 . General. The Block Transfer

activates G9. The output of G9 enables the

Adapter (BTA) control circuit recognizes the

set input of FF3 and on the next high-to-

address and selects the BTA internal regis-

low transition of CLCK-P, FF2 is cleared

ters for reading or writing. It performs

and FF3 is set. The 0 output of FF2 enables

direct data transfers (DDT) transferring

G7 and the 1 output of FF3 enables G10 and

blocks of data to or from the Core Memory

activates G8. G8 generates BTRQ-N which

or other Processor functions and slaves the

is routed to the INFIBUS access circuit

Mag Tape Controller to transfer data to or

causing an interrupt request to be

from the Formatter. The BTA and the Mag

generated to have the data word read out of

Tape Controller are initialized (registers

the Serial I/O. On the next count (seventh)

by the binary decoder U42, the 6 and 7 de-

loaded) simultaneously under CPU control

coder U21 and U51 generates TR07-P which

and afterwards the BTA becomes the master.

activates G7. The output of G7 enables

When initialized for a write operation, the

the clear input of FFl. On the next high-

Formatter indicates ready status to the Mag

to-low transition of CLCK-P, FFl is cleared

Tape Controller and the Mag Tape Control-

and G4 and G5 are disabled. The high out-

ler indicates to the BTA to start transfers.

put of G4 prevents the binary counter U42

When completed, the BTA notifies the Mag

from counting. When the Serial I/O is

Tape Controller to initiate a level 3 inter-

slaved to read out the data word, the ad-

rupt to indicate a completion of a block

dress recognition circuit generates RCBA-N.

transfer to the CPU. When initialized for

RCBA-N activates G13 which resets FF3.

a read operation a similar sequence occurs.

5 - 5 1 9 . If the stop bits of the word from the

5 - 5 2 3 . Detail Analysis (see figure 71).

external device are not present, RDTR-N is

When master reset, MRES-N, is generated

5-73