SERIAL I/O CONTROL GROUP ASYNCHRONOUS DATA TRANSFER CONTROL CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

7 decoder generates TR07-P. TR07-P en-

FF6 activates G8 which, again, generate:,

ables gates G7, G14 and G16 and is also

BTRQ-N to the INFIBUS access circuit for

routed to the data selector/control circuit.

the generation of an interrupt request for

the next data word. Also, the data selector

5-507. When the interrupt is serviced and

control circuit removes DAGN-P which dis-

the serial I/O is slaved and provided with

ables G14.

data, the address recognition circuit gener-

ates AOCK-N which is coupled through

5 - 5 1 1 . The cycle of transferring the next

driver DRl. DRl generates TCBE-N which

word to the external device is repeated as

resets FF6 and is routed to the data selector/

discussed. When all data words required

control circuit which generates the stop

are transferred to the external device, the

bits.

control register circuit removes TOAK-P

which disables G8, preventing interrupt

5-508. The 1 output of FF6 (low) disables

requests from being generated.

G8 and the 0 output of FF6 enables G16.

When TR07-P is generated by the 6 and 7

5 - 5 1 2 . Prior to loading the control register

decoder U21 and U51, TR07-P activates

of the Serial I/O for a read operation, the

G16 which enables the set input of FF7.

particular Serial I/O is cleared as explained

On the next high-to-low transition of

previously. This causes the data selector/

CLCK-P, FF7 is triggered and set. The 1

control circuit to generate DSTS-P which

output of FF7 enables its own clear input

enables G6.

and the set input of FF8. The 0 output of

FF7 activates gates G3 and G15. G3 gener-

5-513. With a read operation control word

ates TRST-N which is routed to the data

stored in the control register circuit, the

selector/control circuit. G15 generates

control register circuit generates TNOT-N

TSFT-P which is routed to the address re-

and RINS-P. TNOT-N presets FF6 and

cognition circuit.

resets FF7 and FF8. RINS-P enables gates

G8, G9, G11 and activates Gl. The 1

5-509. On the next high-to-low transition

output of FF6 enables G8 and the output of

of CLCK-P, FF7 is cleared and FF8 is set.

Gl enables the set input of FFl.

The 0 output of FF7 disables G3 and Gl5.

FF8 generates TSER-N which holds G15

5 - 5 1 4 . On the high-to-low transitron of

activated, disables G16, and activates

CLCK-P, FFl is triggered and set. The 1

G17. G17 generates TRSE-P which is in-

output of the FFl enables G5 and the 0 out-

verted by inverter I2 generating TRSA-N.

put of FFl activates G4. The output of G4

TSER-N and TSFT-P are routed to the

enables the binary counter U42 to count the

address recognition circuit to prevent data

high-to-low level transitions of CLCK-P.

from being loaded into the Serial I/O data

On the sixth count (0110) the binary counter

U42 causes the 6 output of the 6 and 7

to the data selector/control circuit to en-

decoder U21 and U51 to go high which acti-

able data to be serially transmitted to the

vates G5 and G5. The output of G5 and

external device.

CLCK-P activates gate G2. The output of

G2 enables G10 and is inverted by inverter

5-510. Every TR07-P generated to the data

I1 which generates RCBC-N. RCBC-N acti-

selector/control circuit by the 6 and 7 de-

vates G3 which generates TRST-N. RCBC-N

coder U21 and U51 causes one data bit to

and TRST-N are routed to the data selector/

be transmitted to the external device. When

control circuit to clear the data register and

the complete word is transmitted, the data

start bit flip-f lop. This causes the data

selector/control circuit generates DAGN-P

selector/control circuit to remove DSTS-P

which enables G14. The next TR07-P pulse

which disables G6,.

activates G14 which enables the set input

of FF6 and clear input of FF8. On the next

5 - 5 1 5 . On the next high-to-low transition

high-to-low transition of CLCK-P, FF6 is

of CLCK-P, FF2 is set and the 0 output of

set and FF8 is cleared. The 1 output of

FF2 disables G5 and G7 and activities G17.

5-72