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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
circuit controls the transferring of data to
G5 and RLOP-P enables G10. TRAC-N,
or from the external device. Control words
RLPR-N and BARL-N are routed to the data
from the control register circuit enable the
multiplexers U56, U58, U67, and U68.
asynchronous data transfer control circuit
5 - 4 9 7 . The asynchronous data transfer
to perform write or read operations. In a
control circuit generates RCBC-N and
write operation, the asynchronous data
TRST-N. RCBC-N clears the data shift
transfer control circuit controls the con-
register U77 and TRST-N resets FF3. The
version of parallel data in the data selector/
asynchronous data transfer control circuit
control circuit to serial data for transmis-
then generates TRSE-P and TRSA-N. TRSE-P
sion to the external device. In a read opera-
enables G6 and TRSA-N enables the data
tion, the asynchronous data transfer con-
shift register to shift to the left.
trol circuit controls the conversion of
serial data from an external device to
5 - 4 9 8 . Serial data from the external de-
parallel data to be stored in the data
vice is routed to flip-flop FF4, either
selector/control circuit.
directly or via inverter I2. When the start
bit of the word from the external device is
5 - 5 0 3 . Detail Analysis (see figure 70).
received, FF4 is cleared which disables
When the master reset pulse is generated
G5 and activates G10. G5 presents a high
on the INFIBUS or when the status register
to the SDLS input of data shift register U77
is written, the control register circuit
and G10 causes a 0 to be coupled back to
generates RNIN-N and TNOT-N. RNIN-N
the external device.
resets flip-flops FFl, FF2, FF4, FF5, and
activates gate G13 which resets flip-flop
5 - 4 9 9 . The data shift register U77 is
FF3. TNOT-N presets flip-flop FF6 and
clocked which causes it to shift to the
resets flip-flops FF7 and FF8. The 1 out-
left as explained during a write operation
and the serial data is loaded into it. When
put of FF6 enables gate G8.
the start bit is in the DOOS-P position
5 - 5 0 4 . With a write operation control
(high), the set input of FF3 is enabled.
word stored in the control register circuit,
FF3 is set, as explained previously, which
generates DSTS-P and the stop bit of the
RNIN-N, TOTR-N and TOTS-P are gener-
ated. RNIN-N holds FFl through FF5 reset.
word received causes FF4 to be set which
generates RDST-P and RDTR-N. DSTS-P,
TOTR-N activates gate G4 which enables
RDST-P, and RDTR-N are routed to the
the binary counter U42 to be triggered by
asynchronous data transfer circuit which
CLCK-P from the clock generator circuit
removes TRSE-P and TRSA-N.
and TOTS-P enables gate G14. With TNOT-N
high, the preset input of FF6 and reset
5-500. When the Serial I/O is addressed
inputs of FF7 and FF8 are disabled.
to read out data stored in the data shift
register, the address recognition circuit
5-505. When the external device is ready
causes MPXA-P and MPXB-P to go low and
to accept data, the control register circuit
generates BDIN-P. This causes the data
generates TOAK-P which activates G8. G8
multiplexers U56, U58, U67 and U78 to
generates BTRQ-N to the data selector/
couple 1CO and 2CO inputs, DOOS-P
control circuit and to the INFIBUS access
through D07S-P, and the 1Y and 2Y outputs,
circuit which generates an interrupt request.
DDOO-N through DD07-N. BDIN-P strobes
data bus driver/receivers which couples
5 - 5 0 6 . The binary counter U42 is a divide
DDOO-N through DDO7-N to the INFIBUS as
by 16 counter which counts every high-to-
DBOO-N through DB07-N, respectively.
low transition of CLCK-P from the clock
generator circuit. It provides a 4-bit
SERIAL I/O CONTROL GROUP
binary-coded-decimal number to the 6 and
ASYNCHRONOUS DATA TRANSFER
7 decoder U21 and U51. On the sixth
CONTROL CIRCUIT.
count (0110), the 6 and 7 decoder U21
5 - 5 0 2 . General. The Serial I/O control
and U51 6 output enables gates G5 and G6
group asynchronous data transfer control
and on the seventh count (0111), the 6 and
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