SERIAL I/O CONTROL GROUP CONTROL REGISTER CIRCUIT.-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

to couple the lC3 and 2C3 inputs and to

5 - 4 9 4 . TR07-P from, the clock generator

the 1Y and 2Y outputs. This causes TOTR-N

circuit enables G6 and once every seventh

to generate DDOO-N, and DN04-N through

of 16 CLCK-P pulses G6 is activated. The

DN07-N to generate DD04-N through DD07-N

output of G6 activates G7 and when

which are routed to the data bus driver/

TR07-P is removed G6 is disabled which

receivers U59 and U69.

disables G7. The low-to-high transition

output of G6 triggers FFl through FF3.

5-490. BDIN-P strobes the data bus

FF2 remains set which holds G5 disabled,

driver/receivers U59 and U60, and BOLA-P

and FFl is cleared which enables gate G2

strobes the device number bus drivers U60

and disables the set input of FF2. DOOS-P

and U70. This causes the Serial I/O en-

is routed to the set input of FF3 and if

coded device number to be strobed onto the

DOOS-P is high, FF3 remains set which

INFIBUS data lines.

holds G10 disabled and a 1 is indicated to

the external device (first data bit). If

5-491. When the interrupt is serviced the

DOOS-P is low, FF3 is cleared which acti-

Serial I/O is addressed to write data into the

vates G10 and a 0 is indicated to the

data register. Data from the INFIBUS,

external device (SDAT-N). The low-to-

DBOO-N through DB07-N, is inverted by the

high transition output of G7 clocks the data

data bus driver/receivers U59 and U69 in-

shift register U77 which shifts once to the

verters (11 shown) which generates DOOA-P

left and one stop bit (the output of G5 high)

through D07A-P. DOOO-P through D007-P

is shifted into the D07S-P position.. The

are routed to the parallel data inputs, A

cycle is repeated and the data shift register

through H, of data shift register U77, and to

U77 is again shifted to the left and the

the control register circuit. The address

second stop bit is shifted into the data shift

recognition circuit generates AOCK-N and

the asynchronous data transfer control cir-

which activates G5 and G5 presents a low

cuit generates TCBE-N. AOCK-N activates

to the SDLS input of data shift register U77.

gate G7 and TCBE-N presets FFl and FF2.

The 1 output of FFl disables gate G2 and en-

5 - 4 9 5 . The cycle is repeated seven times

ables the set input of FF2. The 0 output of

and the second stop bit will be in the

FF2 disables G5. When AOCK-N is removed,

DOOS-P position which enables gate G3 and

the set input of FF3. Gates G2 and G4 are

G7 is disabled and the low-to-high

activated (DOlS-P through 307S-P are low).

transition output of G7 clocks the data

G2 and G4 activate G3 which generates

shift register U77 which loads it with

DAGN-P. DAGN-P is routed to the asyn-

the parallal data.

chronous data transfer control circuit and

on the next low-to-high transition output

5-492. After the data register is loaded,

of G6 the data shift register is shifted to

the asynchronous data transfer control cir-

the left and the last stop bit is transmitted

cuit generates TRST-N. TRST-N resets FF3

to the external device. G3 is disabled

and the 0 output of FF3 activates G10 (start

(DOOS-P goes low) which removes DAGN-P

bit). The output of G10 activates the TTY

and the asynchronous data transfer control

driver U10, Q4, and T3 and is inverted by

circuit removes, TRSE-P which disables

inverter I3 which removes SDAT-N.

G6 and TRSA-N which prevents the data

shift register U77 from shifting. The se-

5 - 4 9 3 . The asynchronous data transfer

quence is repeated to transfer the next

control circuit then generates TRSE-P and

data word to the external device.

TRSA-N. TRSE-P enables gate G6 and

TRSA-N enables the data shift register to

5 - 4 9 6 . With a control word for a read oper-

shift to the left (D07S-P to DOOS-P). At

ation stored in the control register circuit,

this time, G5 presents a high to the serial

RINS-P, RLOP-P, TWX-N, RLPR-N, and

data left shift (SDLS) input of data shift

BARL-N are generated. RINS-P enables

5-70