SERIAL I/O CONTROL GROUP CONTROL REGISTER CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

SERIAL T/O CONTROL GROUP DATA

5-483.

SERIAL I/O CONTROL GROUP CON-

5-476.

SELECTOR/CONTROL CIRCUIT.

TROL REGISTER CIRCUIT.

5 - 4 8 4 . General. The data selector/control

5 - 4 7 7 . General. The control register cir-

circuit stores data that is to be transmitted

cuit stores control words (determined by

to the external device or received from the

stored software program) which commands

external device. Also, the data selector/

the asynchronous data transfer control cir-

control circuit selects the data that is to

cuit to perform read or write operations.

be placed on the INFIBUS.

5-478. Detail Analysis (see figure 68)

When the master reset pulse is generated

5 - 4 8 5 . Detail Analysis (see figure 69).

on the INFIBUS or when the status register

When the master reset pulse is generated

is written, the address recognition circuit

on the INFIBUS or when the Serial I/O

generates ARES-N. ARES-N clears control

status register is written, the address

recognition circuit generates ARES-N.

FFl and FF2. RNIN-N and TNOT-N are

ARES-N activates gates G8 and G9 and

generated by inverters I2 and I3, and

presets flip-flop FF3. The outputs of G8

routed to the asynchronous data transfer

and G9 reset flip-flops FFl and FF2, re-

control circuit.

spectively. FF3 generates DSTS-P and the

0 output of FF2 enables gate G3 and gate

5-479. When the control register is writ-

G5.

ten into, the data selector/control circuit

presents the control word, DOOA-P through

5-486. With a write operation control word

DOSA-P, and the address recognition cir-

stored in the control register circuit, TOTR-N,

cuit generates ALDC-P. ALDC-P clocks

TOTS-P, TRSR-N, RRDR-N, TRAC-N, EARL-N

the control register and triggers the control

and TDRY-P are generated. TOTS-P enables

flip-flops FFl and FF2. This causes the

gate G5 and G10. TOTR-N, TOTS-P, TRSR-N,

control word to be loaded into the control

RRDR-N, TRAC-N, BARL-N and TDRY are

routed to the input,: of data multiplexers

U56, U58, and U67.

5-480. DCOA-P and DOlA-P are decoded

by inverter I1 and gates G3 and G4. When

5 - 4 8 7 . When the external device is ready

DOOA-P is high (read operation), G3 is

to accept data, the asynchronous data

activated. When DOOA-P and DOlA-P are

transfer control circuit generates BTRQ-N

high (write operation), G4 is activated.

which is routed to the 2Cl input of data

multiplexer U56. Also, the INFIBUS access

5 - 4 8 1 . Gates Gl, G2, G5, G6, single

circuit initiates an interrupt and during the

shot SS1, inverters I2 through I7, and

interrupt cycle, the INFIBUS access circuit

transistor switch Q3 decodes the control

generates BOLA-P and the address recogni-

word stored in the control register U48 and

tion circuit generates MPXA-P, MPXB-P,

control flip-flops FFl and FF2. When a

and BDIN-P.

write control word is stored, TOTR-N,

TOTS-P, TRSR-N, RRDR-N, TRAC-N, BARL-N,

5-488. The Serial I/O device number

and TDRY-P can be generated and routed

DN04-P through DNl l-P is routed to the

to the data selector/control circuit. Also

address recognition circuit and also in-

RWIN-N, TOAK-P, TOTS-P and TOTR-N are

verted by inverters I4 through I11. 14

generated and routed to the asynchronous

through I7 generate DN04-N through DN07-N

data transfer control circuit.

which is routed to the data multiplexers

5-482. When a read control word is stored,

U67 and U78. The outputs of I8 through

RINS-P, RLOP-P, TRAC-N, RLPR-N, and

I11 are routed to the device number bus

BARL-N can be generated and routed to the

drivers U60.

data selector/control circuit. Also, TNOT-N

and RINS-P are generated and routed to the

5 - 4 8 9 . MPXA-P and MPXB-P cause the

asynchronous data transfer control circuit.

data multiplexers U56, U58, U67 and U78

5-69