SERIAL I/O CONTROL GROUP CLOCK GENERATOR CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

activates G13 which sets FF6. The output

activated which enables the load inputs of

of I7 is also inverted by inverter I4 which

dividers U72, U73, and U79. On the next

disables G4. The 0 output of FF6 clears

trigger, the three counters are preloaded.

FF3 and FF4, and activates G8 which clears

Divider U79 is loaded with binary coded 11

FFl.

(1011) where the least significant bit posi-

tions is A and the most significant bit is

5-468. When the address recognition cir-

D. Divider U73 is also loaded with 11 and

cuit generates ADUN-N; ADUN-N is routed

divider U72 is loaded with 14.

through driver DR2 which generates DONE-N

on to the INFIBUS.

5-474. After the dividers U72, U73 and

U79 are preloaded, divider U79 will divide

5-469. SERIAL I/O CONTROL GROUP CLOCK

the output of I1 by five to step divider U73

GENERATOR CIRCUIT.

once (11 to 12). At this time divider U79

is at zero and divider U73 is at a 12 count.

5 - 4 7 0 . General. The clock generator cir-

Divider U79 is now a divide by 16 counter

and divider U73 is effectively a divide by four

cuit is a psuedo random clock generator

used to control the rate of data transfers

counter. In order for divider U73 to step di-

vider U72 once, divider U79 now divides the

(BAUD rate) to and from the external device.

The TTY Controller and the Printer Control-

output of I1 by 16 and divider U73 divides by

four. Divider U72 now steps to a count of 15

ler (ACOC group only) do not use the clock

(1111) which causes the carry output to enable

generator logic. The TTY and Printer Con-

Gl and the QA output of divider U72 to go high.

trollers use an external variable clock that

The QA output of divider U72 is inverted by

is coupled through the clock generator cir-

I3 and the output of I3, CLCK-P, goes low.

c u i t . This external variable clock is used

Therefore, in order to change the state of

to vary the BAUD rate, synchronizing the

CLCK-P from the initial time (preloaded

TTY Controller or Printer Controller to the

BAUD rate of the external device.

counters), the total division is four (U80)

times five (U79) plus the result of four (USO)

times I6 (U79) times four (U73), this equals

5 - 4 7 1 . Detail Analysis (see figure 67).

a division of 276 and causes a CLCK-P pulse

The TTY Controller and Printer Controller

of 11.04 usec duration to be generated.

functions do not use the clock generator

logic. The external variable clock, DSRI-P,

from the TTY Controller or Printer Controller

5 - 4 7 5 . The clock pulse that caused divider

U72 to step to a count of 15, also causes

is coupled through inverters I2 and I3. The

dividers U79 and U73 to return to a count of

output of I3, CLCK-P, is routed to the data

0. With divider U73 at a count of 0, the

selector/control circuit, asynchronous

carry output of divider U73 (low) prevents the

data transfer circuit, and control register

carry output of divider U72 from being gener-

circuit.

ated. Dividers U79 and U73 count 256 (1024

CLKA-N input pulses) additional input triggers.

5 - 4 7 2 . The following discussion pertains

At this time, dividers U79, U73, and U72 are

to the Modem Controller 1 and 2 functions

each at a count of 15 and the carry output of

which receive CLKA-N from the INFIBUS.

divider U79 enables Gl. The carry output of

CLKA-N is a 25 MHz symmetrical signal

U79 also causes the carry output of divider

and is applied to `divider U80 which divides

U73 to be generated which causes the carry

CLKA-N by four (6.25 MHz).

output of divider U72 to be generated. The

carry output of divider U72 activates Gl. The

5 - 4 7 3 . Initially, dividers U72, U73, and

next trigger input to the dividers U79, U73,

U79 contain a random count. Inverter I1

and U72, with Gl activated, causes the

inverts the output of divider U80 clocking

divider to be preloaded, as explained previ-

dividers U72, U73, and U79. Divider U79

ously, a second time. This sequence of events

is always enabled and its carry output en-

causes a 11.04 usec pulse to be generated at

ables divider U73 to count. When dividers

a 19.2 KHz rate (1200 band x 16).

U79, U73 and U72 are fully loaded, Gl is

5-68