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Page Title:
SERIAL I/O CONTROL GROUP INFIBUS ACCESS CIRCUIT |
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 T.O. 31S5-4-368-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
(high) activates G5 which clears FF2.
The 1 output of FF2 disables G3, G14,
INFIBUS ACCESS CIRCUIT.
and G15. G16, enabled by the high
5-458. General.
The INFIBUS access cir-
output of G14, couples PCDA-P to the
INFIBUS or PCDB-P.
cuit performs the function of obtaining ac-
cess to the INFIBUS on the assigned inter-
The 1 output of FF3 enables G5
rupt level when data is to be transferred
5-464.
and activates gate G4 which sets FF4 and
or when an error, while transferring data,
activates gate G10. G10 generates BOLA-P
has occurred.
(waveform F, figure 66) which is routed to
the data selector/control circuit and address
5-459. Detail Analysis (see figure 65).
When the master reset pulse is generated
recognition circuit. The 0 output of FF4
on the INFIBUS or when the status register
disables G2 and the 1 output of FF4 enables
is written, the address recognition circuit
gate G6 and G9 and activates G11. G11
generates ARES-N. ARES-N clears flip-flops
generates BONE-N (waveform G, figure 66)
FF2 through FF5 and activates gate G8 which
which activate G10 and is routed to the
resets flip-flop FFl.
address recognition circuit. BOLA-P also
enables gates G12 and G13 and is inverted
5-460. When a control word, enabling
by inverter I5.
interrupts, is stored in the control register
The output of I5 (low) is delayed 50 nsec
of the control register circuit, BALS-P is
by DLl and then activates G12 which gener-
generated by the control register circuit
ates STRB-N (waveform H, figure 66).
which enables the set input of FFl. BTRQ
or EROR-N (waveform A, figure 66) from the
STRB-N is inverted by inverter I6
5-465.
asynchronous data transfer circuit activates
which generates STRA-P (waveform I,
gate Gl which triggers and sets FFl.
figure 66). STRA-P IS routed to the address
recognition circuit and coupled through
driver DR3 which generates STRC-P (wave-
5-461. Deleted.
form J, figure 66). STRC-P is routed to the
address recognition circuit. STRA-P also
activates G6 which clears FF3 and the 0
output of FF3 (high) is coupled through DRl
which removes SACK-N. STRA-P is also in-
verted by inverter I1 which disables G4.
Normally, within 2 usec after
5-466.
STRB-N is generated, DONE-N (waveform
The Bus Controller senses
5-462.
K, figure 66) is generated by the master
SRL2-N and generates SEL2-N and
function receiving the interrupt. DONE-N
PCDA-P. SEL2-N disables G2 and the
is inverted by inverter I2 which activates
o u t p u t of G 2 (high) enables G3 and
G9 and G11. The output of I2 IS inverted
activates G14 which disables gate
by inverter I3 which disables G4 and G7.
PCDA-P, when received, acti-
G16.
The output of G9 sets FF5 and activates G8
v a t e s G3 which disables gate G5 and
w h i c h r e s e t s F F l . The 1 output of FF5 en-
s e t s F F 3 . The 0 output o f F F 3 d i s -
ables G7. When DONE-S goes high, I2
ables G2 and G15 and is coupled
disables G9 and G11, and the output of
t h r o u g h driver DRl which generates
I3 activates G7 which clears FF4. The 1
SACK-N. T h e output of G15 is coupled
output of FF4 (low) clears FF5 and with
through DR4 which removes SRL2-N.
G11 disabled, G10 is disabled which dis-
ables (G12 and STRB-N is removed.
SACK-N is sensed by the B u s Con-
5-463.
t r o l l e r which causes the bus Controller
to remove SEL2-N. When PCDA-P goes low,
G 3 is disabled and the output of G 3
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