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Page Title: SERIAL I/O CONTROL GROUP ADDRESS RECOGNITION CIRCUIT-CONT.
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T.0, 31S5-4-308-l
TM 11-5805-66.3-14-13
NAVELEX 0967-464-0010
(waveform H, figure 61). The output of G6
(waveforms D through G, figure 63) are
also activates gate G7 which generates
generated as explained previously. With
MPXB-P. (MPXB-P is not used for a control
the data register addressed gate G4 is acti-
register write cycle. ) ACNT-P and RITA-P
vated which generates ADAT-P (waveform
enables G13. When G11 is activated, as
H, figure 63). ADAT-P enables G16 and
explained previously, G13 is activated
activates G18. The output of G18 enables
which generates ALDC-P (waveform I, figure
G17. When G11 is activated as explained
61). ALDC-P is routed out to the control
previously, G17 is activated. The output
register circuit to clock the control register.
of G17, AOCK-N (waveform I, figure 63),
The control register will then be loaded with
is routed to the asynchronous data transfer
the data present on the INFIBUS lines.
control circuit and data selector/control
ADUN-N (waveform J, figure 61) is gener-
circuit to clock the data into the data regis-
ated as explained previously.
ter. ADUN-N (waveform J, figure 63) is
generated as explained previously.
5-452. To read data from the control regis-
ter, the master function address the Serial
5-454.  To read the contents of the data
I/O with the control register address but
register RITE-N, RITA-P, AIZA-P, STRC-P,
RITE-N (waveform B, figure 62) is not
STRA-P, and AMAS-P (waveforms B through
G, figure 64) are generated as explained
generated.  With RITA-P (waveform C,
figure 62) low G10, G13, Gl5 and G18 are
previously.  ADAT-P (waveform H, figure
disabled. I16 inverts the RITA-P (low)
64), is generated which enables G16 and
G18. PITE-N is high for a read cycle and
which enables G16 and activates G19.
with RITA-P low G10, G13, G15 and G18
AILA-P (waveform D, figure 62) and STRC-P
are disabled. I16 enables G16 and G19.
(waveform E, figure 62) are generated as
With AILA-P high for a valid address, G19
explained previously. STRA-P (waveform
is activated which enables G20. STRA-P
F, figure 62) enables G20. When FFl is
and AMAS-P activates G20 which generates
set, AMAS-P (waveform G, figure 62) acti-
BDIN-P (waveform I, figure 64) to the data
vates G20 which generates BDIN-P (wave-
selector/control circuit. BDIN-P strobes
form J, figure 62). G6 is activated, as ex-
the data register data to the INFIBUS data
plained previously, which activates G7,
lines.  When Gil is activated as explained
generating MPXB-P (waveform I, figure 62),
previously, G16 is activated which gener-
to the data selector/control circuit. I5 in-
ates RCBA-N (waveform J, figure 64).
verts the output of G6 which generates
RCBA-N is routed out to the asynchronous
ACNT-P (waveform H, figure 62); however,
data transfer control circuit for reset pur-
ACNT-N is not used during a read cycle.
poses. During a read cycle of the data
MPXB-P selects the control register con-
register, MPXA-P and MPXB-P are not
tents in the data selector/control circuit
generated which selects the data register
and BDIN-P strobes the control register
contents in the data selector/control cir-
data to the INFIBUS data line:; - ADUN-N
cuit. ADUN-N (waveform K, figure 64) is
(-waveform K, figure 62) is generated as
genera ted a s explained previously.
explained previously.
5-455.  During an INFIBUS access cycle,
5-453. To write data into the data register,
BONE-N activates G7 and G8 which gener-
the master function will address the Serial
I/O function with FXY8 16. The X and Y
ates MFXA-P and MPXB-P. MPXA-P and
MFXB-P cause the device number to be
represents the variable Serial I/O address
generated to the INFIEUS during the INFI-
and 8 represents the address of the data
BUS access cycle.
register. Address data, and RITE-N (wave-
form B, figure 63) is placed on the INFIBUS
by the master function. RITE-N enables G16
5-456.  The master reset pulse, MRES-N,
is inverted by inverters I13 and I14. The
and G18 and RITA-F (waveform C, figure 63)
output of I14 activates G14 and the output
enables G13, Gl5, G16, and G18. I16 in-
of G14 is inverted by I15 which generates
verts RITA-P which disables G16 and G19.
AILA-P, STRC-F, STRA-P, and AMAS-P
ARES-N.
5-66

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