SERIAL I/O CONTROL GROUP ADDRESS RECOGNITION CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0367-464-0010

put of I10 is delayed 50 nsec by delay DL2.

serial I/O by writing into the status regis-

The delayed output of DL2 disables G11

ter. The address, AB0l-N through ABl5-N

which disables G15 causing ARES-N to re-

(figure 59, waveform A), and RITE-N (wave-

turn to high. At this time, the 1 output of

form B, figure 59) are placed on the INFI-

FF2 enables gate G12 and inverter Ill in-

BUS. The selected Serial I/O status regis-

verts the low output of DL2 which activates

ter address, FXYO 16 is generated where X

G12. The output of G12, ADUN-N (wave-

and Y make up the variable device number

form I, figure 59), is generated for 50 nsec.

(AB04-N through AB11-N). The inverted

The high output of Ill is inverted by inver-

AB04-N through AB11-N inputs are applied

ter I12I then delayed 50 nsec by delay DL3

to the address comparators and inverted

which disables G12. ADUN-N is routed

AB12-N through AB14-N input activate G3.

to the INFIBUS access circuit where it will

The inverted ABl5-N input is coupled

generate DONE-N to indicate a completion

through DRl and with the output of G3 and

to the master function.

the address comparators high, the set input

of FFl high. At the same time, with ABOl-N

5-450. To read the status register of the

through AB03-N high and inverted by inver-

Serial I/O, the cycle is similar to a status

ters 12, 14 and 16 which enables gate G5.

register write except RITE-N (waveform B,

If ABOl-N through AB03-N are not a valid

figure 60) and its inverse RITA-P (waveform

C, figure 60) are not generated. AILA-P

The output of G2, AILA-P, is low which

(waveform D, figure 60) must be present to

disables the set input of FF2. When a

indicate a valid address and STRA-P (wave-

valid address is detected, G2 is disabled

form F, figure 60) is generated at the same

and AILA-P is high. At the same time,

time as STRC-P (waveform E, figure 60).

Inverter I7 inverts RITE-N, generating

STRA-P enables G20. ASUS-P and MPXA-P

RITA-P (waveform C, figure 59). RITA-P

are generated as explained previously.

enables gates G10, G13, G15 and G18.

MPXA-P selects the status data in the data

Inverter I16 inverts RITA-P which disables

selector/control circuit. With RITA-P low,

gates G16 and Gl9. STRC-P (waveform E,

figure 59) from the Serial I/O Control Group

G13, G15, and G18 are disabled. RITA-P

INFIBUS access circuit is coupled through

is also inverted by I16 which enables G16

driver DR2 which activates gate G9. The

and activates Gl9. The output of G19 en-

output G9 triggers and sets FFl. AMAS-P

ables G20 and when AMAS-P is generated,

(waveform F, figure 59) is generated by

as explained previously, G20 is activated

FFl which activates G5. Inverter I3 in-

generating BDIN-P (waveform J, figure 60).

BDIN-N is routed to the data selector/control

verts the output of G5 generating ASUS-P

circuit to strobe the status data to the

(waveform G, figure 59). The output G5

also activates gate G8 which generates

infibus data lines. G11 will be activated

MPXA-P. AMAS-P is inverted by inverter

50 nsec after AMAS-P is generated but does

I8, disables the reset input of flip-flop

not activate any gates. ADUN-N (wave-

FF2 and enables gate G20. At this time,

form K, figure 60) is generated as explained

AILA-P is high (valid address) and the set

previously.

input of FF2 is enabled. After the 50 nsec

delay of delay DLl, Inverter I9 inverts the

5-451. After the status register is read,

delayed output of I8 and triggers and sets

the control register is loaded (written into)

FF2. The output of I9 also activates gate

for a read or write operation with the exter-

G11. The output of G11 activates Gl5

nal device being controlled by the Serial

which activates gate G14. The output of

I/O function. The address recognition

G14 is inverted by inverter I15 which gener-

cycle is the same as discussed except, gate

ates ARES-N (waveform H, figure 59).

G6 will be activated for a control register

ARES-N resets the infibus access circuit,

address. RITE-N, RITA-P, AILA-P, STRC-P,

control register circuit, asynchronous data

STRA-P, and AMAS-P (waveforms A through

transfer control circuit and data selector/

G, figure 61) are generated as explained

control circuit. The high output of I9 is

previously. The output of G6 is inverted

also inverted by inverter I10. The low out-

by lnverter I5 which generates ACNT-P

5-65