SERIAL I/O CONTROL GROUP ADDRESS RECOGNITION CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

Whenaddress F8OX l6 (1,1,1,1,/1,0,0,0,/

5-445. Detail Analysis (see figure 58).

0,0,0,0,/X,X,X,X,) is sensed on the INFI-

The address bus receivers (11 shown)

BUS address lines, address recognition

invert ABOl-N through ABI5-N (ABOO-N, 0

occurs and the operation determined by the

bit position is not used for function address).

condition of the RITE-N line and the inter-

Inverted AB04-N through AB11-N are ap-

nal register selected is performed.

plied to the address comparators (Gl shown)

where it will be compared with the jumper

5-441. The Modem Controller 1 is assigned

encoded address, DN04-P through DN11-P

address F93X l6 where X is any hexidecimal

(device number), from the data selector/

number between 0 and F which allows the

control circuit, AB12 -N through ABl5-N are

appropriate internal register to be addressed.

low for Serial I/O control group function

Whenaddress F93X l6 (1,1,1,1,/1,0,0,1,/

addresses. Inverted ABOl-N through AB03-N

0,0,1,1,/X,X,X,X,) is sensed on the INFI-

are decoded to select one of the three inter-

BUS address lines, address recognition oc-

nal registers.

curs and the operation determined by the

5-446. A typical operation starts with the

condition of the RITE-N line and the inter-

status register being written into which

nal register selected is performed.

clears the selected Serial I/O. Afterwards,

under control of the stored software pro-

5-442. The Printer Controller (ACOC Group

gram, status is tested (read out) by the

only) is assigned address F8lX l6 where X

master function to check the condition of

is any hexidecimal number between 0 and

the selected Serial I/O and the external

F which allows the appropriate internal

device. The control register is then loaded

with the read or write operation to be per-

F81X 16 (l,l,l,l,/1,0,0,0,/0,0,0,1,/

formed with the external device being slaved.

X,X,X,X,) is sensed on the INFIBUS ad-

dress lines, address recognition occurs

5-447. If a write operation is to be per-

and the operation determined by the condi-

formed, the Serial I/O is slaved (addressed)

tion of the RITE-N line and the internal

to select the data register which is then

loaded with the data. With the write oper-

ation loaded into the control register, the

5-443. The Modem Controller 2 (ACOC

selected Serial I/O function presents the

Group only) is assigned address F94X l6

data to the external device. If a read oper-

where X is any hexidecimal number between

ation is to be performed, the selected Serial

0 and F which allows the appropriate inter-

I/O function will strobe the data to the

nal register to be addressed. When address

INFIBUS data lines.

F 9 4 X 16 (1,1,1,1,/1,0,0,1,/0,1,0,0,/

X,X,X,X,) is sensed on the INFIBUS ad-

5-448. The data selector/control circuit

dress lines, address recognition occurs

always applies the jumper encoded device

and the operation determined by the condi-

number, DN04-P through DN11-P, to the

tion of the RITE-N line and the internal

address comparators. The inverted AB04-N

through ABl l-N inputs are compared with

the jumper encoded device number and if

5-444. Each of the four Serial I/O's have

a match occurs, the set input of flip-flop

three internal registers; the status register,

FF1 will be enabled. When both inputs to

control register, and data register. When

each of the address comparators are at the

X is equal to 0 (O,O,O,O,) the status regis-

same level, the output will be high. All

ter of the selected Serial I/O is addressed.

of the outputs of the address comparators,

When X is equal to 6 (0, 1, 1, 0,) the control

gate G3 and driver DRl must be high for

the set input of FF1 to be enabled.

dressed. When X is equal to 8 (l,O,O,O,)

5-449. Initially, a master function slaves

the data register of the selected Serial I/O

the selected Serial I/O to clear the selected

is addressed.

5-64