SERIAL I/O CONTROL GROUP ADDRESS RECOGNITION CIRCUIT

T.O. 31S5-4-308-1

11-5805-663-14-13

NAVELEX 0967-464-0010

activates G12 which activates G10 and

e Alarm Control and VF Comm

5-432.

G14. The output of G10 resets FF2 and

Link ES not ready to accept the data word,

G14 generates EROR-N. EROR-N is routed

enerates WDNR-N, STSl-N, and STS2-N.

to the Parallel I/O INFIBUS access circuit

NR- activates gate Gl5, and STSl-N

to initiate an interrupt to indicate the

and STS2-N disable G6. The output of G15

Alarm Control and VP Comm Link is not

activates G14 which generates EROR-N.

ready.

EROR-N is routed to the Parallel I/O

INFIBUS access circuit to initiate an in-

5-436. If the Alarm Control and VF Comm

terrupt for the error. The output of G15 is

Link does not present the data word within

inverted by inverter I5 which generates

300 msec after SS4 is triggered, SS4 resets

WDNR-N. WDNR-N disables G4 and G6

which activates G9. The output of G9 pre-

and is also routed to the Parallel I/O data

sets FF4 which generates RTER-N which is

input and selector circuit.

routed to the Parallel I/O data input and

selector circuit. RTER-N also activates

gate G12 which activates G10 and G14.

G10 resets FF2 and G14 generates EROR-N

5-433. The Alarm Control and VF Comm

which is routed to the Parallel I/O INFIBUS

Link presents a data word to the parallel

access circuit. The Parallel I/O INFIBUS

I/O which causes the data input and selec-

access circuit initiates an interrupt to in-

tor circuit to generate RDST-N (waveform

F, figure 57) and RDSP-P (waveform G,

dicate a read timing error.

figure 57). RDSP-P triggers FF4 (FF4 re-

5-437. If the previous data word presented

mains cleared), and activates gate G10

by the Alarm Control and VF Comm Link is

which resets FF2. This causes RDRC-N

not read out of the Parallel I/O before the

and RDRH-P to be removed and G9 to be

next data word is presented, the previous

disabled 50 nsec after FF2 is reset.

word is destroyed and a read timing error

5-434. RDST-N and RDSP-P are removed

occurs. FF3 is not reset by G8, as ex-

after 1.0 usec causing RF3 to be triggered

plained previously, which holds the set

and set, and G10 to be disabled. The 1

input of FF4 enabled. When RDSP-P is

generated by the Parallel I/O data input

output of FF3 enables the set input of FF4

and also, activate G13. The output of G13 is

and selector circuit, FF4 is triggered and

set which generates RTER-N. As explained

coupled through DR1 which generates PDSA-N.

PDSA-N is routed to the Parallel I/O

previously, EROR-N is generated which

INFIBUS access circuit. The Parallel I/O

initiates an interrupt to indicate an over-

INFIBUS access circuit initiates an inter-

run error.

rupt to have the data word read out. When

the Parallel I/O is slaved to have the data

5-438. SERIAL I/O CONTROL GROUP

ADDRESS RECOGNITION CIRCUIT.

word read out, the Parallel I/O address re-

ceiver and recognition circuit generates

DRBB-N (waveform I, figure 57). DRBB-N

5-439. General. The address recognition

circuit recognizes the Serial I/O address

activates G8 which resets FF3, causing

PDSA-N to be removed. When DRBB-N is

(device number) that is placed on the INFI-

removed, G8 is disabled which triggers

BUS address lines when slaved by a master

and sets FF2. This causes RDRC-N and

function. It decodes a portion of the address

RDRH-P to be generated. This cycle is

to select any of the three internal registers

repeated for each data word to be trans-

and depending on the condition of the

ferred.

RITE-N line, it performs a read or write

cycle.

5-435. If the Alarm Control and VF Comm

Link is not ready to have a data word read

5-440. The TTY Controller is assigned ad-

out, it generates RDNA-N. RDNA-N dis-

dress F8OX l6 where X is any hexidecimal

ables gate G11 which generates RDNR-N.

number between 0 and F which allows the

RDNR-N disables the set input of FF3 and

appropriate internal register to be addressed.

5-63