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Page Title: PARALLEL I/O READ/WRITE CONTROL STATUS CIRCUIT.
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T.O. 31S5-4-308-1
T M 11-5805-663-14-13
NAVELEX 0967-464-0010
gers and clears FFl which removes WBAR-N/
which generates DBRA-P, DBRB-P, and
WBAS-P.  With WBAS-P low. G13 is dis-
DBRC-P, respectively. At the same time,
abled causing PDSA-N to be removed,
the Parallel I/O data input and selector
With WBAR-N high, G4 and G6 is acti-
circuit generates DOOA-N through Dl5A-N,
vated.
G6 triggers single-shot SS2
which remains set for 2.0 usec. The
representing the Parallel I/O address,
output of G4 activated  ate
G5, The
output of G5 is inverterted  b y
which are routed to data bus driver/
inverter
I1 which generates WDGA-N.
receivers U69, U70, U79 and U80, DBRA-P,
WDGA-N is
routed to the Alarm Control
and
VF
DBRB-P, and DBRC-P strobe data bus
Comm Link.
driver/receivers U69, U70, U79, and U80
5 - 4 2 8 . When the Alarm Control and VF
which couples DOOA-N through D15A-N to
INFIBUS data lines DBOO-N through DB15-N.
Comm Link is ready to accept the data word,
WDDC-P is generated which activates ex-
clusive-OR g a t e Gl. T h e o u t p u t o f G 1
PARALLEL I/O READ/WRITE CON-
activates G4 and the output of G4 activates
TROL STATUS CIRCUIT.
g a t e G 5 .  The output of G5 is inverted by
i n v e r t e r I1 w h i c h g e n e r a t e s W D G A - N ( w a v e -
5 - 4 2 4 . G e n e r a l .  The Parallel I/O read/
write control status circuit controls the
form I, figure 56).  WDGA-N is routed to
the Alarm Control and VF Comm Link.
transferring of data to or from the Alarm
Control and VF Comm Link. It controls
5-429. After 2.0 usec, SS2 resets and
read and write operations with the Alarm
triggers single-shot SS3. The 0 output of
Control and VF Comm Link and provides
error indications for timing errors and over-
SS3 is inverted by inverter I2 which gener-
ates WDST-P (waveform J,  figure 56).
run conditions.
WDST-P is routed to the Alarm Control and
5 - 4 2 5 .  Detail Analysis (see figure 55).
VF Comm Link causing it to accept the data
When the master reset pulse is generated on
w o r d .  The Alarm Control and YF Comm Link
the INFIBUS or when the Parallel I/O status
removes WDDC-P which disables G1. The
register is written, the Parallel I/O data
high-to-Low transition output of G1 triggers
output and control register circuit gener-
S S l .  The 1 output of SSl activates G2
ates GRSA-K (waveform A, figure 56) and
which presets FF1.  FFl generates WBAS-P
GRSC-P (waveform B, figure 56). GRSA-N
and WBAR-N and the cycle for- transferring
resets flip-flop FF4 and activates gate G8
data to the Alarm Control and VF Comm
which resets flip-flop FF3. GRSC-P acti-
Link is repeated for the next data word.
vates gate G2 and the output of G2 presets
5-430.
flip-flop FFl.  FFl then generates WBAR-N
When the Parallel I/O control
(waveform C, figure 56) and WBAS-P
register is loaded with a read operation
(waveform D, figure 56). WBAR-N disables
control word, the Parallel I/0 data output
gates G4 and G6, and WBAS-P enables gate
and control register circuit generates
G13.
WRCO=P (waveform A, figure 57), CROA-P
(waveform B, figure 57), and CROS-P
5-426. When a write control word is loaded
(waveform C, figure 57). WRCO-P and
CROA-P activate gate G3 which presets
in the Parallel I/O data output and control
f l i p - f l o p F F 2 . CROS-P enables G13 and
register circuit, CR1S-P (waveform E,
the set input of FF2.
figure 56) is generated. CRlS-P enables
gates G4 and G14 and activates gate G13.
T h e o u t p u t o f G 1 3 generates P D S A - N .
5 - 4 3 1 .  The 1 output of FF2 is inverted by
inverter I3, triggers single-shot SS4, and
5-427. P D S A - N  is routed to the Parallel
enables G9 after a 50 nsec delay by DLl.
INFIBUS  access circuit which causes
I/O
I3 generates RDRC-N (waveform D, figure
i t t o i n i t i a t e a n i n t e r r u p t .  WDDC-N
57) and SS4 disables gate G9 for 300 msec.
from the Alarm Control and VF Comm Link
is normally a high, which a c t i v a t e d e x -
The 1 output of FF2 is inverted by inverter
c l u s i v e - O R gate G1. The output of Gl
J4 which generates RDRC-N (waveform E,
e n a b l e s G4.  W h e n t h e P a r a l l e l I / O i s
p r e s e n t e d with a data word, the Paral-
figure 57). RDRC-N is routed to the
l e l I/O data output and control register
A l a r m Control and VF Comm Link to
c i r c u i t generated W D R B - N .  WDRB-N  trig-
initiate a read operation.

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