PARALLEL I/O DATA OUTPUT AND CONTROL REGISTER CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

cuit then generates ADAT-P (waveform C,

generates CROA-P (waveform A, figure 52)

figure 53) and AWRT-P (waveform D, figure

which is routed to the input of control

53). ADAT-P enables G9 and AWRT-P

activates G9 which generates WDBR-N

I/O read/write control status circuit. When

(waveform E, figure 53). WDBR-N triggers

ACNT-N (waveform C, figure 52) and AWRT-P

and loads the output data register U57 and

(waveform D, figure 52) are generated, G11

U76 with the data word. Also, WDBR-N

is activated which generates WRCQ-P

is routed to the Parallel I/O read/write

(waveform D, figure 52), AS discussed,

control circuit. This causes WBAS-P

WRCO-P triggers and loads control register

(waveform A, figure 53) to be removed

U66 with the read control word and the

which disables G9. G9 removes WDBR-N

control register generates CROS-P (wave-

(waveform E, figure 53) and the outputs of

form E, figure 52) which is routed to the

the output data registers U57 and U76 are

Parallel I/O read/write control status

coupled through data drivers U62, U63 and

circuit. CR2S-P is generated to enable

U72 (DRI shown) which generates ODOO-P

interrupts as discussed.

through OD11-P (waveform F, figure 53).

ODOO-P through OD11-P represents the

5-419. When the Parallel I/O is slaved to

data word which is routed to the Alarm

read its control register, the Parallel I/O

Control and VF Comm Link Function.

address receives and recognition circuit

generates AABL-P and ARED-P which enable

5 - 4 2 1 . When the Parallel I/O is slaved

G14. The Parallel I/O INFIBUS access cir-

to read data out of its data register, the

cuit then generates STRA-P which activates

Parallel I/O address receiver and recogni-

G14. The output of Gl4 enables G12, G13

tion circuit generates AABL-P (waveform

and G15. The Parallel I/O address re-

A, figure 54) and ARED-P (waveform B,

ceiver and recognition circuit then generates

figure 54). AABL-P and ARED-P enable

AMAS-P which activates G12 causing

G14. The Parallel I/O INFIBUS access

DBRA-P to be generated. At the same time,

circuit then generates STRA-P (waveform

the Parallel I/O data input and selector

C, figure 54) which activates G14. The

circuit generates DOOA-N through D15A-N,

output of Gl4 enables G12, G13 and G15.

representing the control word, which is

The Parallel I/O address receivers then

routed to data bus driver/receivers U69,

generate AMAS-P (waveform D, figure 54)

U70, U79 and U80. DBRA-P strobes data

bus driver/receivers U70 and U80 which

and ADAT-P (waveform E, figure 54).

AMAS-P activates G12 which generates

couple DOOA-N through DO5A-N, DO8A-N,

DBRA-P (waveform F, figure 54) and

and D09A-P to the INFIBUS data lines,

DBOO-N through DB05-N, DB08-N, and

ADAT-P activates G13 and G15 which

DB09-N.

generates DBRB-P (waveform G, figure 54)

and DBRC-P (waveform H, figure 54),

5 - 4 2 0 . To have data loaded into the

respectively. At the same time, the Parallel

Parallel I/O data register, the Parallel

I/O data input and selector circuit generates

I/O must first be reset. Then the Parallel

DOOA-N through D15A-N , representing

I/O control register is loaded with a write

data, which are routed to data bus driver/

control word. This causes WBAS-P (wave-

receivers U69, U70, U79, and U80.

form A, figure 53) and CRlS-P (waveform

DBRA-P, DBRB-P, and DBRC-P strobes the

B, figure 53) to be generated, as discussed

data bus driver/receivers which cause

previously, which enables G9. When the

the data to be routed onto the INFIBUS

Parallel I/O is slaved to write data into

data lines DBOO-N through DBl5-N.

its data register, DBOO-N through DB11-P,

representing the data word, are present

5 - 4 2 2 . When the Parallel I/O performs

on the INFIBUS. DB00-N through DB11-N

an interrupt, the Parallel I/O address

are inverted and routed to the output data

(device number) is placed on to the

INFIBUS data lines. The Parallel I/O

receivers U69, U70 and U80. The Parallel

INFIBUS access circuit generates BOLA-P

I/O address receiver and recognition cir-

and BOLA-P activates G12, G13 and G15

5-61