PARALLEL I/O DATA OUTPUT AND CONTROL REGISTER CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

verted by inverter Ill which generates

5-416. When the Parallel I/O is slaved to

GRSC-P. Or, when the Parallel I/O is

load a write operation control word into the

slaved to write its status register, the

control register, DBOO-N through DB05 -N,

Parallel I/O address receiver and recogni-

representing the control word are on the

tion circuit generates AWST-N (waveform

INFIBUS. DBOO-N through DBOS-N are in-

A, figure 49) and AWRT-P (waveform B,

verted by data bus driver/receiver U80 and

figure 49). AWST-N enables gate G10 and

routed to the inputs of control register U66.

AWRT-P is inverted by inverter I13 which

Inverter I7 and gates G4 and G7 decode the

a c t i v a t e s G10. The output of G10 activates

inverted DBOO-N and DBOl-N bits. For a

G8 which generates GRSA-N (waveform C,

write operation, both DBOO-N and DBOl-N

figure 49) and I11 generates GRSC-P (wave-

are low which causes G4 to be disabled and

form D, figure 49). GRSA-N and GRSC-P

G7 to be activated. G4 presents a low and

are routed to the Parallel I/O read/write

G7 presents a high to the inputs of control

control status circuit for reset purpose.

This causes the Parallel I/O read/write

receiver and recognition circuit generates

control status circuit to generate WBAS-P

ACNT-N (waveform A, figure 51) which

(waveform E, figure 49) which enables

enables gate G11. Afterwards, the Parallel

gate G9. GRSA-N also resets control regis-

I/O address receiver and recognition cir-

cuit generates AWRT-P (waveform B, figure

ter U66 (flip-f lop FF2 shown).

51) which is inverted by I13. The output

5-415. When the Parallel I/O is slaved to

of I13 activates G11 which generates

read out its status register, the Parallel

WRCO-P (waveform C, figure 51). WRCO-P

I/O address receiver and recognition cir-

triggers and loads the control register U66

cuit generates AABL-P (waveform A, figure

with the control word. Also, WCRO-P is

50) and ARED-P (waveform B, figure 50)

routed to the Parallel I/O, read/write control

which enables gate G14. The Parallel

status circuit.

I/O INFIBUS access circuit generates

STRA-P (waveform C, figure 50) which

5-417. The control register U66 generates

activates G14. The output of G14 enables

CRlS-P (waveform D, figure 51) for a write

gates G12, G13 and G15. The parallel I/O

operation and CR2S-P (waveform E, figure

address receiver and recognition circuit

51) which is routed to the Parallel I/O

then generates AMAS-P (waveform D, figure

INFIBUS access circuit to enable interrupts.

50) and AWST-N (waveform E, figure 50).

Also, gate G2 and inverters I3 through I6

AMAS-P activates G12 which generates

and I8 invert the outputs of control register

U66 and generate CROO-N through CRO5-N

DBRA-P (waveform F, figure 50). AWST-N

is inverted by inverter I14 which activates

(waveform F, figure 51) which are routed to

the Parallel I/O data input and selector

G15 and G15 generates DBRC-P (waveform

G, figure 50). At the same time, the

circuit.

Parallel I/O data input and selector circuit

generates DOOA-N through Dl5A-N (repre-

senting status data) which are routed to

the data bus drivers/receivers U69, U70,

U79, and U80. DBRA-P strobes data bus

driver/receiver U70 and U80 which couples

5-418. When the Parallel I/O is slaved to

DOOA-P through DOSA-N, D08A-N, and

load a read operation control word into the

DOSA-N to the INFIBUS data lines DBOO-N

control register, the cycle performed is

through DBOS-N, DBOI-N, and DBO9-N.

similar to the cycle performed when loading

DBRC-P strobes data bus driver U79 which

a write operation control word. The differ-

couples Dl2A-N through D15A-N to the

ence is that for a read operation control

INFIBUS data lines DB12-N through DB15-N.

word DBOO-N is low and DBOl-N is high

After the transfer is completed, STRA-P

(on the INFIBUS) which causes G4 to be

is removed which causes the status data

activated and G7 to be disabled. G4

to be removed from the INFIBUS.

5-60