PARALLEL I/O AlA3A10 INFIBUS ACCESS CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

AWST-N is generated by G5, G12 is acti-

inverter I9 which activates gate G9. G9

vated. The output of G12, MPXA-P, is

generates ADUN-N (waveform H, figure 42)

routed to the Parallel I/O data output and

which causes the Parallel I/O INFIBUS ac-

selector circuit to select the status data

cess circuit to generate DONE-N, indicating

that is to be placed on the INFIBUS data

a completed data transfer. Inverter I10

lines.

then inverts the output of I9 and after the

SO nsec delay of delay DL3, G9 is disabled

5-395. When the Parallel I/O INFIBUS

which removes ADUN-N (high).

access circuit is requesting INFIBUS access,

BONE-N is low. BONE-N activates G12

5 - 3 9 1 . To perform a read operation of the

and G13 which generate MPXA-P and MPXB-P,

data register, the master function places

respectively. With MPXA-P and MPXB-P

the Parallel I/O address on the address

both high, the Parallel I/O data output and

lines and RITE-N will be high. The address

control register circuit generates the Paral-

is recognized, G6 is enabled and G3 gener-

lel I/O device number which is strobed to

ates AABL-P as explained previously. I11

the INFIBUS data lines.

inverts the high RITE-N input and disables

G7 and G10. Inverter I12 inverts the out-

5 - 3 9 6 . PARALLEL I/O AlA3A10 INFIBUS

put of Ill and generates ARED-P (waveform

A, figure 43) which enables gate G11.

ACCESS CIRCUIT.

5-392. The remainder of the read operation

5 - 3 9 7 . General. The Parallel I/O INFIBUS

is similar to the write operation, except

access circuit generates a level 1 interrupt

when I7 inverts the delayed output of I6,

INFIBUS access request and, under control

of the Bus Controller, allows the Parallel

G11 is activated. G11 generates DRBB-N

(waveform B, figure 43) and after I9 inverts

I/O to gain INFIBUS access. The level 1

the delayed output of I8, G9 is activated.

interrupt is generated whenever the Parallel

I10 inverts the output of I9 which disables

I/0 requests the INFIBUS to transfer data

G11. 50 nsec later, G9 is disabled re-

or whenever the Parallel I/O detects an

moving ADUN-N.

error during a data transfer.

5-393. The control register write operation

5-398. Detail Analysis (see figure 44).

is similar to the data register write opera-

Initially, the Parallel I/O data output and

tion, except G4 is enabled as explained

control register circuit generates GRSA-N

previously and then activated by AMAS-P

which clears the Parallel I/O INFIBUS

which generates ACNT-N. ACNT-N acti-

access logic circuit. GRSA-N is generated

vates gate GI3 which generates MPXB-P.

when a master reset pulse, MRES-N, is

The control register read operation is simi-

received or when a write status register

lar to the data register read operation, ex-

operation occurs. GRSA-N clears flip-flops

cept ACNT-N is generated and G13 is

FF2 through FF5 and activates gate G11

activated which generates MPXB-P. MPXB-P

which resets FFl.

is used by the Parallel I/O data input and

selector circuit during the read operation

5 - 3 9 9 . When an INFIBUS access is re-

to select the control register data to be

quired, the Parallel I/O data output and

placed on the INFIBUS data lines.

control register circuit generates CR2S-P

(waveform A, figure 45) which enables FFl

5 - 3 9 4 . The status register write operation

to be set when triggered. Whenever a word

is similar to the other write operations, ex-

is to be written into or read from the Parallel

cept G5 is activated. G5 generates AWST-N

I/O (under control of the stored software

to the Parallel I/O data output and control

program), the Parallel I/O read/write control

status circuit generates PDSA-N (waveform

reset for the Parallel I/O function. AWST-N

C, figure 45). Whenever the read/write

activates gate G12 which generates MPXA-P.

control status circuit detects an error,

The status register read operation is simi-

EROR-N (waveform D, figure 45) is generated.

lar to the other read operations, except when

PDSA-N or EROR-N activates gate Gl. The

5-57