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Page Title: PARALLEL I/O A1A3A10 DATA INPUT AND SELECTOR CIRCUIT.
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T.O. 31S5-4-308-l
TM 11-5805-663-14-13
NAVELEX 0967-464-0010
output of Gl is inverted by inverter I1 which
5-402. STRB-N is inverte
triggers FF1. The output of FFl activates
which generates STRA-P (wav
gate G5 if SELl-N is high (no other function
45). STRA-P activates gate
requesting INFIBUS access). The output of
FF3. The 0 output of FF3 en
G5 sets FF2 and disables gates G2 and G6.
G5 and the i output of FF
The output of FF2 enables G2 and G6 and
G8. Clearing FF3 causes SACK-N to return
also activates gate G4. The output of G4
to high. After data is transferred, DONE-N
is coupled through driver DRl which gener-
(waveform M, figure 45) is received.
ates SRLl-N (waveform E, figure 45).
DONE-N is inverted by inveter I3 which
generates BDNA-P (waveform N, figure 45)
5-400. The Bus Controller receives SRLl-N
BDNA-P activates G13, G14, and is a
and returns SELl-N, (waveform F, figure
inverted by inverter I2. The output of Gl
45) and the precedance pulse PCDA-P (wave-
sets FF5 and activates G11 which resets
form G, figure 45). SELl-N disables G5
FFl. The output of I2 disables gates G7
which enables G6 and activates G2. Gate
and G10. With FF5 set, G10 is enabled
G3 is disabled by the output of G2. G3 is
and when DONE-N is removed, BDNA-P
normally enabled and will couple PCDA-P
will go low which disables G13 arid G14.
to the INFIBUS as PCDB-P if an INFIBUS
The output of I2 now activates G10 which
access is not being requested. When an
clears FF4. The output of G14 (high) dis-
INFIBUS access is being requested G3 is
ables G12 which causes BOLA-P to go low.
disabled and PCDB-P is not coupled to
BOLA-P now disables G16 which removes
the INFIBUS.
STRB-N. Clearing FF4 disables G9 and
G14, clears FF5, and enables G5.
5-401.  PCDA-P, when received, activates
5-403. If DONE-N is not received within
G6 which disables gate G8 and sets FF3.
2 usec after STRB-N goes low, the Bus
The 0 output of FF3 disables gates G4
Controller generates QUIT-N. Inverter I4
and G5 and is coupled through driver DR2
inverts QUIT-N which activates gate G15
which generates SACK-N (waveform H,
(G15 enabled by BOLA-P during the normal
figure 45).  The Bus Controller detects
c y c l e ) .  The output of G15 clears FF3 and
SACK-N and removes SELl-N. G5 is again
FF4 and activates G11 which resets FFl.
enabled by SELl-N (high) but disabled by
Inverter 15 inverts the output of I4 which
the 0 output of FF3.  The 1 output of FF3
disables G7 to allow G15 to clear FF4.
enables gate G8. When PCDA-P returns
to low G6 is disabled and activates G8.
5-404. PARALLEL I/O A1A3A10 DATA INPUT
The output of G8 clears FF2 which disables
AND SELECTOR CIRCUIT.
G2, G4, and G6. With G2 disabled, G3
is enabled and PCDA-P can be coupled to
5-405. General.  The Parallel I/O data
the INFIBUS. The 1 output of FF3 also
input and selector circuit receives data
activates gate G7. The output of G7 sets
from the Alarm Control and VF Comm Link
FF4 and activates gate G12. The 0 output
function and selects the data that is to
of FF4 disables G5 and the 1 output of FF4
be placed on the INFIBUS data lines.
enables gates G9 and G13 and activates
VF Comm
Data from the Alarm Control a
gate G14 (FFS cleared). G14 generates
data
Link is temporarily stored by
BONE-N (waveform I, figure 45) and acti-
input register and the data selectors
vates G12 which generates BOLA-P (wave-
select one of four following data input
form J, figure 4.5).  BOLA-P and BONE-N
groups: data from the Alarm Control
enable the device number to be strobed to
and VF Comm Link function, control regis-
the INFIBUS data lines. BOLA-P also
ter contents, anti Parallel l/O status, or
enables gates G15 and G16 and is inverted
the Parallel I/O address (device number).
by inverter I7. The output of I7 is delayed
Detail Analysis (see figure 46).
5-406.
50 nsec by delay DLl. The output of DLl
The input data register is controlled by the
activates G16 generating STRB-N (wave-
form K, figure 45).

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