PARALLEL I/O AlA3A10 ADDRESS RECEIVERS AND RECOGNITION CIRCUIT-CONT.

T.O. 31S5-4-308-1

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5 - 3 8 6 . Detail Analysis (see figure 41).

Gate G3 will be disabled if the correct

The device number connector J3 connec-

combination of A01A-P, A02A-P and

tions determine the Parallel I/O address

A03A-P are received to select one of

(device number). DN04-N through DN11-N,

the Parallel I/O internal registers.

device number bits, are routed to the

Parallel I/O data input and selector cir-

cuit to be placed on the INFIBUS data

5 - 3 8 9 . To perform a write operation to

lines when the Parallel I/O is requesting

the Parallel I/O data register, the master

a level 1 INFIBUS access. The device

function generates the address (waveform

number inverters (14 shown) generate

A, figure 42), data, and strobe on the

DA04-P through DA11-P. AB0l-N through

INFIBUS and generates RITE-N (waveform

AB15-N from the INFIBUS address lines

B, figure 42). The address will be recog-

are inverted by the address bus receivers

nized which enables FFl to be set, as

U10, U20, U29, and U40 (11 shown) which

explained previously. G3 generates

generate A01A-P through Al5A-P.

AABL-P (waveform C, f i g u r e 4 2 ) a n d e n a b l e s

the set input of flip-flop FF2. RITE-N is

inverted by inverter I11 which enables

5-387. A04A-P through A11A-P are applied

to the address recognition exclusive-nor

G7 and G10. The output of I11 is also

gates U19, U28, and U33 (Gl shown)

inverted by inverter I12 which disables

gate G11 causing ARED-P to go low. If the

where they are compared with the lumper

Alarm Control and VF Comm Link is ready to

encoded device number (DA04-P through

a c c e p t d a t a , WBAR-N is low which disables

D A l l - P ) . If there is a match at the inputs,

g a t e G 7 . The high output of G7 enables

the corresponding outputs of address re-

gate G8. The parallel I/O INFIBUS access

cognition exclusive-nor gates U19, U28,

circuit generates STRA-P (waveform D, fig-

and U39 will be high. Also, for address

ure 42) which is applied to driver DR2. The

recognition, A12A-P must be high which is

output of DR2 is coupled through driver DR3

coupled through driver DRl. In addition,

then delayed 50 nsee by delay DL4. The

A13A-P, A14A-P and A15A-P must be high

output of DL4 activates gate G8 which

which activates gate G2. The combined

triggers and sets FF1. If the Alarm Con-

outputs of address recognition exclusive-

trol and VF Comm Link function is not

nor gates U19, U28, and U39, driver DRl,

ready to accept data, WBAR-N from the

and G2 will be high which places a high

read-write control status circuit is high

at the set input of flip-flop FF1.

w h i c h a c t i v a t e s G 7 . The output of G7

now disables G8 until the Alarm Control

5-388. Inverters I2, I3, and I5, and

and VF Comm Link Function is ready

gates G3 through G6 decode A01A-P,

When ready, WBAR-N returns to low dis-

A02A-P, and A03A-P to select the control,

abling G7 which activates G8.

status, or data registers in the Parallel

I/O data output and control register cir-

cuit. To select the control register, A01A-P

and A02A-P are high and A03A-P is low.

Gate G4 is enabled by A0lA-P and AO2A-P

and the high output of I5. G4 is act!-

vated and generates ACNT-N when FF1

i s s e t . To select the status register,

A0lA-P, A02A-P and A03A-F are all low

and the high outputs of I2, I3, and I5

enable G5. When FFl set;, G5 is acti-

vated which genetates AWST-N . To

select the data register, A01A-P and

A02A-P are low and A03A-P is high. G6

is enabled by the outputs of I2 and I3

and A03A-P. When FF1 is set, G6 will

activated

which

generates

ADAT-P.

5-56