AUTOLOAD AlA3A9 ROM AND DATA CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

5-370. AUTOLOAD AlA3A9 ROM AND

BDNA-P a second time. This second

DATA CIRCUIT.

BDNA-P pulse activates G25 generating

BEND-N and activates G36. The output

5 - 3 7 1 . General. The Autoload ROM and

of G36, BCLK-N (waveform M, figure 38),

data circuit strobes the Autoload address

sets FF11, and activates G35 which holds

to the INFIBUS data lines during a direct

ONLN-P high and BONL-N low until

data transfer, strobes the Autoload device

BDNA-P returns to low. The 1 output of

number (address) to the INFIBUS data

FF11 enables G34. When BDNA-P re-

lines during a level 1 interrupt data

turns to low, the output of I3 returns to

transfer, or strobes the ROM nibbles

high which activates G34. The output of

data register information to the INFIBUS

G34 clears FF9 which disables G35.

data lines in word or byte format when

Disabling G35 causes BONL-P to return

the Autoload is being slaved (addressed).

to low and disables G28 causing ONLN-P

to return to low. The 0 output of FF9

5 - 3 7 2 . Detail Analysis (see figure 39).

activates G37 which clears FF11.

During a direct data transfer RLDS-P

(waveform A, figure 38) is high and

5-368. If during a direct data transfer

AONL-N goes low and the start address

BDNA-P is not received within 2 usec

is placed on the DBOO-N through DBl5-N

after STRB-N is generated, the Bus Con-

INFIBUS data lines. When RLDS-P is

troller generates QUIT-N. QUIT-N is

high, the 0 volt and 5 volt inputs to data

inverted by inverter I4 and because

multiplexes U59 and U69 are coupled to

BDNA-P was not received FF3 is still set.

bus drivers U60 and U70. When AONL-N

When the output of I4 goes high G23 is

activated which presets FF6 and disables

(waveform F, figure 38) goes low, gate

gate G18. This high output of G18 is

G18 is activated which strobes data bus

inverted by inverter I6 which causes

drivers U60 and U70 causing DB08-N,

ABRT-N to go low. The 0 output of FF6

DBO9-N and DB11-N through DB15-N to

clears FF2 and FF3. The 1 output of

go low and DB10-N to remain high.

FF3 now disables G23 which enables G18

During a direct data transfer RLDR-N is

and resets FF6 which activates G28

also low and when ONLN-P (waveform E,

causing ABRT-N to return to high. The

figure 38) goes high the first time,

output of 14 is also inverted by inverter

ABOl-N and AB02-N, are strobed to the

15 to disable G5 until FF2 is cleared.

INFIBUS address lines, causing ABOl-N

and AB02-N to go low for the duration of

ONLN-P. This action strobes address

5 - 3 6 9 . If, during a level 1 interrupt

0006 16 onto the INFIBUS address lines.

data transfer, BDNA-P is not received

RITE-N is also generated at this time.

within 2 usec after STRB-N is generated

by the Bus Controller, QUIT-N is gen-

5 - 3 7 3 . During a level 1 interrupt data

era ted. QUIT-N is inverted by I4 and

transfer, INTS-P (waveform J, figure 38)

because BDNA-P was not received FF9

is high and BONL-N goes low and the

is still set, thereby enabling G22.

Mag Tape Unit number is placed on the

When BQTA-P goes high, G22 is acti-

DBOO-N through DB03-N INFIBUS data

vated which disables G18 and resets

l i n e s . When INTS-P is high the 5 volt

FF5. The high output of G18 activates

inputs and the inputs determined by the

G25, causing BEND-N to go low. In

positions of switches S3 and S4 are

addition, the output of G18 is inverted

by I6 causing ABRT-N to go low. When

coupled through the data multiplexer U39

BOTA-P returns to low G22 is disabled

and routed to data bus driver U40. When

and FF5 IS preset which activates G18

BONL-N (waveform L, figure 38) goes

causing ABRT-N to go high. When FF5

low, gate G21 is activated which strobes

r e s e t s , FF8 and FF9 are cleared. The

data bus driver U40 causing DBOO-N and

Output of I4 is also inverted by I5 which

DBO4-N to remain high and DB02-N and

disables G31 until FF8 is cleared.

DB03-N to go to the levels determined

5-53