AUTOLOAD AlA3A9 ROM AND DATA CIRCUIT-CONT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

by S3 and S4. When Mag Tape Unit No.

STA4-P, and STA5-P are low. This

1 will be used to load the tape program,

causes the outputs of ROM4 to assume

switches S3 and S4 are in the down po-

a pre-programmed value (nibble 1).

sition which causes DBOO-N through

STA2-P also enables gate G2 which is

activated by STAB-P (waveform C, fig-

DB03-N to remain high when BONL-N

goes low. When Mag Tape Unit No. 2

ure 40). The output of G2 clocks the

will be used to load the tape program S3

outputs of ROM 4 in to the ROM nibbles

is in the down position and S4 is in the

data register U68. The N100-N through

up position which causes YB00-N,

N103-N outputs of the ROM nibbles data

DB02-N and DB03 -N to remain high and

DBOl-N to go low when BONL-N goes

multiplexer U69 to the data bus drivers

low During a level 1 interrupt data

U70.

transfer RLDR-N is high and when ONLN-P

5-377. When STA3-P (waveform D, fig-

goes high, ABOO-N and ABOl-N remain

high.

ure 40) goes high, the output of inverter

I9 goes low activating G3. The output

of Gl is still low and the output of G3

5-374. When the Autoload function is

being addressed, the selected ROM

is high (address bits ABOl-N through

outputs are clocked into the ROM nibbles

AB07-N remain unchanged), which

data register and then strobed to the

causes the outputs of ROM 4 to assume a

INFIBUS data lines in word or byte for-

second pre-programmed value (nibble 2).

mat. The address bits AB03-N through

STA3-P also enables G4 which is acti-

AB07-N are coupled through inverters I1

vated by STAB-P. The output of G4

through I5 and address bits ABOl-N and

clocks the outputs of ROM 4 into the

AB06-N are coupled through inverters of

ROM nibbles data register U68. The

address bus driver receivers U20 (18

N200-N through N203-N outputs of the

typical). AOlA-P through A07A-P are

ROM nibbles data register U68 are

routed to ROM 4 which is enabled by

coupled through data multiplexer U59

ERM4-N from the Autoload address recog-

to the data bus drivers U60.

nition and ROM select circuit.

5-378. When STA4-P (waveform E, fig-

ure 40) goes high, the output of inverter

5-375. When the Autoload address

recognition and ROM select circuits

16 goes low activating G1. The output

recognize the Autoload address on the

of G1 is high and the output of G3 re-

turns to low because STA3-P has returned

INFIBUS address lines, AMAS-P (wave-

form A, figure 40) goes high enabling

to low (address bit A301-N through AB07-N

gates G17 and G22. Also, RLDS-P and

remain unchanged). The outputs of Gl

INTS-P are low, which allows nibble

and G3 now cause the outputs of ROM 4

bits N100-N through N103-N, N200-N

to assume a third pre-programmed value

(nibble 3). STA4-P also enables gate

through N203-N and N400-N through

G10 which is activated by STAB-P. The

N403-N to be coupled through the data

output of G10 activates gate G11 which

multiplexers U69, U59 and U39. If a

activates gate G8. The output of G8

word (16-bits or four 4-bit nibbles) is

clocks the outputs of ROM 4 into the

to be strobed to the INFIBUS data lines,

ROM nibbles data register U48. The

BYTE-N is high and is inverted by in-

N300-N through N303-N outputs of ROM

verter I12. This low output of I12 dis-

nibbles data register U48 are routed to

ables gates G6, G7, G12 and G13 and

the data bus drivers U50.

is inverted by inverter I13. This high

output of I13 enables gates G2, G4,

5-379. When STA5-P (waveform F, fig-

G11, and G15.

ure 40) goes high, the output of inverter

I7 goes low activating Gl and G3 (ad-

5-376. When STA2-P (waveform B, fig-

dress bits ABOl-N through AB07-N re-

ure 40) goes high, the outputs of gates

main unchanged). The outputs of G1

G1 and G3 are low because STA3-P,

5-54