AUTOLOAD AlA2A9 INFIBUS ACCESS CIRCUIT

T.O. 31S5-4-308-l.

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

D, figure 38) to go low. The output

G24, G26 and G37 are enabled and gate

of G5 sets FF3 and activates gate

G29 is activated which enables gate G32.

G28 causing ONLN-N (waveform E,

INTS-P activates G32 which sets FF10.

figure 38) to go low. The 0 output of

The 0 output of FFlO clears FF7. The 1

FF3 disables G10 which disables Gl.

output of FF10 enables gate G17 and

The 1 output of FF3 enables gates G9,

G33 and activates G26. The output of

G11, G12, G23 and G25, enables FF6

G26 is coupled through driver DR3 which

to be preset, and activates gate G7.

generates SRLl-N (waveform K, figure 38).

The output of G7 activates gate G8

In response to SRLl-N the Bus Controller

causing AONL-N (waveform F, figure

causes SELl-N to go low which disables

3 8 ) t o g o l o w . AONL-N also activates

G32. The high output of G32 now enables

G28, generating ONLN-P. When

G33 and activates G17 which disables

PDCA-P returns to low, G2 is dis-

G16. Also, the Bus Controller generates

abled which activates G3. The output of

the precedence pulse a second time.

G3 clears FFl which disables G2.

When the precedence pulse, PCDA-P,

g o e s h i g h , G 3 3 is a c t i v a t e d w h i c h s e t s

FF8. The 1 output of FF8 enables G30

nsec after ONLN-P goes high,

5-363.

STRA-P (waveform G, figure 38) goes

and activates gates G21 and G31. The

high which activates G11 and enables

output of G21 activates G20. The output

of G20 is coupled through DR2 causing

gate G27. STRA-P is also inverted by

SACK-N to go low a second time. The

inverter I2 which disables G5 (ONLN-P

output of G31 sets FF9 and activates G28

remains high because AONL-N still Pow).

Activating G11 clears FF2. With AONL-N

which causes ONLN-P to go high a

and ONLN-N low, the address 0006 16 is

second time. The 0 output of FF9 dis-

ables G29 which disables G32. The 0

strobed to the INFIBUS address lines

output of FF8 also disables G24 and G26.

and the Autoload address FB00 is strobed

The output of G24 is inverted by I7 which

to the INFIBUS data lines.

sets FF7. Setting FF7 activates G37

5-364. When the direct data transfer is

which ensures FF11 is cleared.

Dis-

abling G26 causes SRLl-N to return to

complete, the addressed function (Core

high. T h e 1 o u t p u t o f F F 9 e n a b l e s g a t e s

Memory Controller) generates DONE-?!

which causes the Autoload control cir-

G22, G25, G27, G35, and G36. When

cuit to generate BDNA-P (waveform H,

PCDA-P returns to low, G33 is disabled

figure 38). When BDNA-P goes high,

which activates G30. The output of G30

clears FF10.

G9 and G12 are activated. The output

of G12, ACLK-N (waveform I, figure 38),

sets FF4 and disables G7 and the output

50 nsec after ONLN-P goes high

5-366.

of G9 holds G8 activated. BDNA-P also

the second time, STRA-P goes high a

activates G25 causing BEND-N to be

second time activating G27 which clears

generated. Setting FF4 enables gate

FF8. The output of FF8 enables G26 and

G7. BDNA-P is also inverted by in-

the 1 output of FF8 disables G21 which

verter I3. When BDNA-P returns to low,

causes SACK-N to go high. T h e o u t p u t

of FF9 disables G24, G29, and G37. The

the output of I3 returns to high which

1 output of FF9 activates G35 which

activates G6. The output of G6 clears

causes BONL-N (waveform L, figure 38)

FF3, Clearing FF3 disables G7, G9,

to go low which holds ONLN-P high

G11, and G12 causing ACLK-N and

Clearing FF8 also disables G31. With

AONL-N to return to high. Clearing

FF3 also activates gate G13 which

clears FF4.

ACLK-N also causes INTS-P

5-365.

(waveform J, figure 38) from the Autoload

c o n t r o l circuit to be generated. With

FF8, FF9 and FF11 still cleared, gates

5-52