AUTOLOAD AlA2A9 INFIBUS ACCESS CIRCUIT.

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

l i n e s . The Autoload INFIBUS access

to gate G6. When AB08-N, AB09-N,

circuit also places and monitors vari-

and AB11 -N through AB15-N are low and

ous signals on the INFIBUS to ensure

AB10-N is high G1 through G5 are dis-

a proper data transfer occurs.

abled and G6 is activated. This high

level output of Gl through G6 is routed

5 - 3 6 1 . Detail Analysis (see figure 37).

to the set input of flip-flop FFl. When

When the Autoload control circuit

STRB-N goes low, it is inverted by in-

receives the master reset pulse, MRES-N,

verter I9 causing STRA-P to go high.

ARES-P goes high which is inverted by

The output of I9 is also coupled through

inverter I8. The output of I8 clears

driver DRl. This high output of DRl

flip-flops FFl through FF4 and FF8

allows FFl to be set and is also coupled

through FF11. The 1 output of FF3 resets

through driver DR2. The output of DR2

flip-flop FF6. QUIT-N (normally high)

is inverted by inverter I10. This neg-

is inverted by inverter I4 which presets

ative going edge out of I10 causes FF1

to set. When FFl sets AMAS-P and

FF5.

AMAR-N are generated which activates

the Autoload control circuit. Also, when

5 - 3 6 2 . With FF2, FF3 and FF4 reset,

FFl sets, G15 is activated. The output

gate G10 is activated which enables

of G15, ERM4-N, enables the ROM in

gate G1. If no other function is re-

the Autoload ROM and data circuits.

questing a direct data transfer, SELD-N

ERMl-N through ERM3-N are not gen-

will be high, also enabling Gl. 140

erated because switches Sl and S2 are

msec after the Autoload signal is detec-

always in the up position. When STRB-N

ted on the INFIBUS, RLDS-P (waveform

returns to high, the output of DRl goes

A, figure 38) goes high, activating Gl

low which resets FFl.

which sets FFl. The 0 output of FFl

ensures flip-flop FF7 is cleared. The 1

5-358. When the Autoload INFIBUS

output of FFl activates gate G14. The

access circuit requires STRB-N to be

output of G14 is coupled through driver

generated, ONLN-P goes high which

DRl causing SRLD-N (waveform B, fig-

enables gate G7. ONLN-P is also in-

ure 38) to go low. The Bus Controller

verted by inverter I11 then delayed 50

detects SRLD-N and causes SELD-N to

nsec by DL7 which activates G7, caus-

go low which disables Gl and the BUS

ing STRB-N to go low 50 nsec after

Controller generates the precedence

ONLN-P goes high. When ONLN-P goes

pulse, PCDA-P. Disabling Gl enables

low, G7 is disabled and STRB-N returns

qate G2 and activates gate G15 which

to high. The output of I11, GEST-N, is

disables gate G16. When the prece-

also routed to the Autoload control

dence pulse, PCDA-P (waveform C,

circuit.

figure 38), is received, G2 is acti-

vated which sets FF2. The 0 output

5-359. AUTOLOAD AlA2A9 INFIBUS

of FF2 disables G10 which in turn

ACCESS CIRCUIT.

d i s a b l e s Gl. In addition, the 0 out-

put of FF2 disables G14 which causes

5 - 3 6 0 . General. The Autoload INFIBUS

SRLD-N to return to high, and dis-

ables gate G24. The output of G24

access circuit, under control of the

is inverted by inverter I7 which sets

Autoload control circuit, causes a direct

FF7. The output FF7 activates G37

data transfer to take place which stobes

which ensures FF11 is cleared. The

the address 0006 16 onto the INFIBUS

output of FF7 also activates gate

address lines. At the same time, the

G13 which ensures FF4 is cleared.

Autoload address FB00 is strobed to the

The 1 output of FF2 enables gate G3

INFIBUS data lines. After the direct

and activates gates G5 and G19, The

data transfer, the Autoload control cir-

output of G19 activates gate G20.

cuit causes the Autoload INFIBUS access

The output of G20 is coupled through

Circuit to generate a level 1 interrupt

driver DR2 causing SACK-N (waveform

which strobes onto the INFIBUS data

5-51