AUTOLOAD AlA3A9 ADDRESS RECOGNITION AND ROM SELECT CIRCUIT

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

vates G12 at a 6.25 MHz rate. The

DONE-N causes STRB-N (Autoload

output of G12 is inverted by inverter I11.

INFIBUS access logic circuits) to go

The output of I11, STAB-P (waveform

high which causes AMAS-P to go low and

figure 35), enables gate G2 at a 6.25

AMAR-N to go high. When AMAS-P goes

MHz rate and clocks the Autoload ROM

low FF5 and FF7 are reset. The Autoload

and data circuit.

INFIBUS access circuit generates BCLK-N

in response to BDNA-P. When BCLK-N

5-351. When the Autoload address rec-

goes low, G6 is activated which resets

ognition and ROM select circuit recog-

FF4.

nizes the Autoload address on the

INFIBUS address lines, AMAS-P goes

5 - 3 5 3 . If DONE-N is not received or

high and AMAR-N goes low for the dura-

generated within 2 usec after STRB-N

tion of STRB-N. When AMAS-P is high,

goes low, QUIT-N (Autoload INFIBUS

FF5 and FF7 are enabled to be set.

access logic circuit) causes ABRT-N to

When AMAR-N (waveform D, figure 35)

go low which activates G5 and G6. The

goes low, SS2 is triggered and the 80

output of G5 resets FF3 and the output of

nsec positive pulse out of SS2 is routed

G6 resets FF4.

to and sets the first stage of the S-bit

5-354. AUTOLOAD AlA3A9 ADDRESS

shift register U65. The trailing edge of

the SS2 output sets FF8. The next neg-

RECOGNITION AND ROM SELECT

ative going edge out of G9, after FF8

CIRCUIT.

sets, sets FF9 (waveform E, figure 35)

which activates G11. The output of G11

5 - 3 5 5 . General. The Autoload address

(waveform F, figure 35) triggers the S-bit

recognition and ROM select circuit de-

shift register U65 five times generating

tects the Autoload address on the INFIBUS

STA2-P (waveform G, figure 35), STA3-P

address lines (Autoload being slaved

(waveform H, figure 35), STA4-P (wave-

after level 1 interrupt request), generates

form I, figure 35), and STA5-P (wave-

signals to select the ROM in the Auto-

load ROM and data circuit, receives

form J, figure 35). STA5-P enables gate

G2 to be activated by STAB-P. The out-

STRB-N from the INFIBUS and routes

STRB-N to the INFIBUS.

put of G2, SSRM-P (waveform K, figure

35) is routed to the Autoload ROM and

data circuit. The trailing edge of the

5-356. Detail Analysis (see figure 36).

Switches Sl and S2, inverters I12 and

output of G2 sets FF5 causing SRDS-P

I13, and gates G8 through Gl5 deter-

to go high. The output of FF5 is inverted

by inverter I4, delayed 50 nsec by DL2

mine the level of the ROM select signals

and then inverted by inverter I5. Also,

ERM1-N through ERM4-N. Switches Sl

when AMAR-N goes low, gate G7 is

and S2 are al-ways in the up position.

This causes the outputs of I12 and I13

activated which enables gate G3. The

to activate G14 which enables G15. If

output of I5 is inverted by inverter I6

and activates G3. The output of I6 is

Sl and S2 were both in the down position,

delayed 50 nsec by delay DL3 which dis-

G8 would be activated which would

enable G9. If Sl was in the up position

ables G3 50 nsec after it was activated.

and S2 was in the down position, G10

The output of G3 is coupled through

would be activated which would enable

driver DR2 and onto the INFIBUS as

G11. If Sl was in the down position and

DONE-N. The output of DR2 is also in-

S2 was in the up position, G12 would be

verted by I8. The output of I8, BDNA-P

activated which would enable G13.

is routed to the Autoload INFIBUS access

logic circuit and inverted by I7 to en-

5-357. Address bits AB08-N through

sure FF6 is preset.

AB15-N are coupled through inverters I1

through I8. The outputs of I1 through

5-352. The negative going edge of

I15 are routed to gates G1 through G5

A1H5-P sets FF7 which activates G4.

and the outputs of I6 through I8 are routed

output of G4 resets FF8 and FF9.

5-50