CPU CENTRAL TIMING CONTROL CIRCUIT - TM-11-5805-663-14-130092

T.O. 31S5-4-308-l

TM 11-5805-663-14-13

NAVELEX 0967-464-0010

which removes SACK-N, and enables G10,

write data into a register. When the CPU

G19, and G21.

is in the run mode, the CPU central timing

control continuously cycles to execute the

stored microcode program.

5-279. If the transfer of data on the

INFIBUS is not completed within'2 usec

5-284. Detail Analysis (see figure 27).

after STRB-N is generated, the Bus Con-

When the master reset pulse, MRES-N, is

troller generates QUIT-N. QUIT-N is

received from the INFIBUS, the CPU control

inverted by inverter I4 which activates

circuit generates RSTl-N (waveform A,

G19. The output of I4 is also inverted

figure 28) and the CPU microcode register

by inverter 17 which disables G17

circuit generates M32T-P (waveform B, fig-

and G20. The output of G19 sets FF5

ure 28). RSTl-N presets flip-flop FFl and

which enables G4 and also routes BAES-P

M32T-P enables gate G4. The 1 output of

to the CPU control circuit to indicate an

FFl activates gates G2 and G5, The output

abort condition. The 0 output of FF5 clears

of G2 is coupled through driver DRl and G5

FF4 and the 0 output of FF4 activates G4.

generates CKOO-P (waveform C, figure 28).

The 1 output of FF4 disables G8 and G14.

CKOO-P is routed to the CPU control circuit.

The output of G4 clears the command reg-

The low output of DRl is inverted by inverter

ister U53 which frees the INFIBUS.

15 which generates CKME-P (waveform D,

figure 28). Inverter 18 inverts CKME-P gen-

5-280. Normally, before 2 usec after

erating CMEN-N (waveform E, figure 28)

STRB-N is generated, the addressed Proces-

which resets FF4 and is routed to the CPU

sor function responds by generating DONE-N

address recognition circuit. CMEN-N also

which indicates a completed data transfer.

disables G5 which removes CKOO-P (wave-

The CPU address recognition circuit senses

form C, figure 28). The pulse width of

DONE-N and generates DUNP-P (waveform

CKOO-P is determined by the inherent delays

K, figure 27). DUNP-P activates G4 and G5

of G2, DRl, 15, and 18.

and is inverted by inverter 12. The output of

G4 clears command register U53 which frees

5-285. Delay DL3 delays the low output of

the INFIBUS. The output of 12 disables G14

DR1 15 nsec and the delayed output (15) is

and G20.

then inverted by inverter 12. The output of

12, CKML-P (waveform F, figure 28), is

5-281. If a read command is loaded in com-

routed to the CPU microcode register circuit

mand register U53, G5 is enabled as ex-

and enables gate G6.

plained previously. DUNP-P now activates

G5 and G4. The output of G5 sets flip-flop

5-286. After the 30 nsec delay of DL3, the

FFl which generates RCLK-N (waveform L,

low output of DL3 (30) is inverted by in-

figure 27). RCLK-N is routed to the CPU

verter 16. The output of 16, CKRD-P (wave-

address recognition circuit which causes the

form G, figure 28)) is routed to the CPU

CPU to load the data into receive register.

control circuit and CPU register file circuit.

The output of G4 clears the command regis-

CKRD-P also enables G4 and activates G6.

ter which frees the INFIBUS.

The output of G6, XSET-N (waveform H, fig-

ure 28), is routed to the CPU register file

5-282. CPU CENTRAL TIMING CONTROL

circuit.

CIRCUIT.

5-287. After the 45 nsec delay of DL3, the

low output of DL3 (45) is inverted by inverter

5 - 2 8 3 . General. The CPU central timing

13. The output of 13 activates G4 which

control circuit generates the timing pulses

disables G2 and G5. The high output of G2

required by the various CPU circuits in

is coupled through DRl. The high output of

executing the stored microcode program.

DRl is inverted by 15 which removes CKME-P

When the CPU is in the halt mode, the CPU

(waveform D, figure 28) and is inverted by

address recognition circuit triggers the CPU

I8 which ensures FF4 is reset and generates

central timing control circuit to cycle when

CMEN-N (waveform E, figure 28).

the CPU is addressed to read data from or

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